Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 58 Preliminary  2015 Microchip Technology Inc.
REGISTER 3-9: FENR: FLOATING POINT EXCEPTIONS AND MODES ENABLE REGISTER; 
CP1 REGISTER 28
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
— — — —
ENABLES<4:1>
VZOU
7:0
R/W-x U-0 U-0 U-0 U-0 R-x R/W-x R/W-x
ENABLES<0>
— — — —FS RM<1:0>
I
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11-7 ENABLES<4:0>: FPU Exception Enable bits
These bits control whether or not a trap is taken when an IEEE exception condition occurs for any of the five
conditions. The trap occurs when both an enable bit and its corresponding cause bit are set either during an
FPU arithmetic operation or by moving a value to the FCSR or one of its alternative representations.
bit 11 V: Invalid Operation bit
bit 10 Z: Divide-by-Zero bit
bit 9 O: Overflow bit
bit 8 U: Underflow bit
bit 7 I: Inexact bit
bit 6-3 Unimplemented: Read as ‘0’
bit 2 FS: Flush to Zero control bit
1 = Denormal input operands are flushed to zero. Tiny results are flushed to either zero or the applied format's
smallest normalized number (MinNorm) depending on the rounding mode settings.
0 = Denormal input operands result in an Unimplemented Operation exception.
bit 1-0 RM<1:0>: Rounding Mode control bits
11 = Round towards Minus Infinity (
– )
10 = Round towards Plus Infinity (
+ )
01 = Round toward Zero (0)
00 = Round to Nearest