Datasheet
2015 Microchip Technology Inc. Preliminary DS60001320B-page 561
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 30-7: MIIM CLOCK SELECTION
REGISTER 30-31: EMAC1MCFG: ETHERNET CONTROLLER MAC MII MANAGEMENT
CONFIGURATION REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
RESETMGMT — — — — — — —
7:0
U-0 U-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CLKSEL<3:0>
(1)
NOPRE SCANINC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 RESETMGMT: Test Reset MII Management bit
1 = Reset the MII Management module
0 = Normal Operation
bit 14-6 Unimplemented: Read as ‘0’
bit 5-2 CLKSEL<3:0>: MII Management Clock Select 1 bits
(1)
These bits are used by the clock divide logic in creating the MII Management Clock (MDC), which the IEEE
802.3 Specification defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz.
bit 1 NOPRE: Suppress Preamble bit
1 = The MII Management will perform read/write cycles without the 32-bit preamble field. Some PHYs
support suppressed preamble
0 = Normal read/write cycles are performed
bit 0 SCANINC: Scan Increment bit
1 = The MII Management module will perform read cycles across a range of PHYs. The read cycles will start
from address 1 through the value set in EMAC1MADR<PHYADDR>
0 = Continuous reads of the same PHY
Note 1: Table 30-7 provides a description of the clock divider encoding.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
MIIM Clock Select EMAC1MCFG<5:2>
TPBCLK5 divided by 4 000x
TPBCLK5 divided by 6 0010
TPBCLK5 divided by 8 0011
TPBCLK5 divided by 10 0100
TPBCLK5 divided by 14 0101
TPBCLK5 divided by 20 0110
TPBCLK5 divided by 28 0111
TPBCLK5 divided by 40 1000
TPBCLK5 divided by 48 1001
TPBCLK5 divided by 50 1010
Undefined Any other combination