Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 53
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 3-3: CONFIG3: CONFIGURATION REGISTER 3; CP0 REGISTER 16, SELECT 3
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
r-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 R-0 R-1 R-0 R-0 R-0 R-1 R/W-y
— IPLW<1:0> MMAR<2:0> MCU ISAONEXC
(1)
15:8
R-y R-y R-1 R-1 R-1 R-1 U-0 R-1
ISA<1:0>
(1)
ULRI RXI DSP2P DSPP —ITL
7:0
U-0 R-1 R-1 R-0 R-1 U-0 U-0 R-0
— VEIC VINT SP CDMM — —TL
Legend: r = Reserved bit y = Value set from Configuration bits on POR
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: This bit is hardwired as ‘1’ to indicate the presence of the Config4 register
bit 30-23 Unimplemented: Read as ‘0’
bit 22-21 IPLW<1:0>: Width of the Status IPL and Cause RIPL bits
01 = IPL and RIPL bits are 8-bits in width
bit 20-18 MMAR<2:0>: microMIPS Architecture Revision Level bits
000 = Release 1
bit 17 MCU: MIPS
®
MCU™ ASE Implemented bit
1 = MCU ASE is implemented
bit 16 ISAONEXC: ISA on Exception bit
(1)
1 = microMIPS is used on entrance to an exception vector
0 = MIPS32 ISA is used on entrance to an exception vector
bit 15-14 ISA<1:0>: Instruction Set Availability bits
(1)
11 = Both MIPS32 and microMIPS are implemented; microMIPS is used when coming out of reset
10 = Both MIPS32 and microMIPS are implemented; MIPS32 ISA used when coming out of reset
bit 13 ULRI: UserLocal Register Implemented bit
1 = UserLocal Coprocessor 0 register is implemented
bit 12 RXI: RIE and XIE Implemented in PageGrain bit
1 = RIE and XIE bits are implemented
bit 11 DSP2P: MIPS DSP ASE Revision 2 Presence bit
1 = DSP Revision 2 is present
bit 10 DSPP: MIPS DSP ASE Presence bit
1 = DSP is present
bit 9 Unimplemented: Read as ‘0’
bit 8 ITL: Indicates that iFlowtrace
®
hardware is present
1 = The iFlowtrace
®
is implemented in the core
bit 7 Unimplemented: Read as ‘0’
bit 6 VEIC: External Vector Interrupt Controller bit
1 = Support for an external interrupt controller is implemented.
bit 5 VINT: Vector Interrupt bit
1 = Vector interrupts are implemented
bit 4 SP: Small Page bit
0 = 4 KB page size
bit 3 CDMM: Common Device Memory Map bit
1 = CDMM is implemented
bit 2-1 Unimplemented: Read as ‘0’
bit 0 TL: Trace Logic bit
0 = Trace logic is not implemented
Note 1: These bits are set based on the value of the BOOTISA Configuration bit (DEVCFG0<6>).