Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 521

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family

bit 6 TXABAT: Message Aborted bit

(2)

1 = Message was aborted

0 = Message completed successfully

bit 5 TXLARB: Message Lost Arbitration bit

(3)

1 = Message lost arbitration while being sent

0 = Message did not loose arbitration while being sent

bit 4 TXERR: Error Detected During Transmission bit

(3)

1 = A bus error occured while the message was being sent

0 = A bus error did not occur while the message was being sent

bit 3 TXREQ: Message Send Request

TXEN =

1: (FIFO configured as a Transmit FIFO)

Setting this bit to ‘1’ requests sending a message.

The bit will automatically clear when all the messages queued in the FIFO are successfully sent

Clearing the bit to ‘0’ while set (‘1’) will request a message abort.

TXEN = 0: (FIFO configured as a Receive FIFO)

This bit has no effect.

bit 2 RTREN: Auto RTR Enable bit

1 = When a remote transmit is received, TXREQ will be set

0 = When a remote transmit is received, TXREQ will be unaffected

bit 1-0 TXPR<1:0>: Message Transmit Priority bits

11 = Highest Message Priority

10 = High Intermediate Message Priority

01 = Low Intermediate Message Priority

00 = Lowest Message Priority

Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits

(CiCON<23:21>) = 100).

2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.

3: This bit is reset on any read of this register or when the FIFO is reset.