Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 52 Preliminary  2015 Microchip Technology Inc.
REGISTER 3-2: CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
r-1 R-0 R-0 R-1 R-1 R-1 R-1 R-0
— MMU Size<5:0> IS<2>
23:16
R-1 R-0 R-0 R-1 R-1 R-0 R-1 R-1
IS<1:0> IL<2:0> IA<2:0>
15:8
R-0 R-0 R-0 R-0 R-1 R-1 R-0 R-1
DS<2:0> DL<2:0> DA<2:1>
7:0
R-1 U-0 U-0 R-1 R-1 R-0 R-1 R-1
DA<0> — —PCWRCAEPFP
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the Config2 register.
bit 30-25 MMU Size<5:0>: Contains the number of TLB entries minus 1
001111 = 16 TLB entries
bit 24-22 IS<2:0>: Instruction Cache Sets bits
010 = Contains 256 instruction cache sets per way
bit 21-19 IL<2:0>: Instruction-Cache Line bits
011 = Contains instruction cache line size of 16 bytes
bit 18-16 IA<2:0: Instruction-Cache Associativity bits
011 = Contains 4-way instruction cache associativity
bit 15-13 DS<2:0>: Data-Cache Sets bits
000 = Contains 64 data cache sets per way
bit 12-10 DL<2:0>: Data-Cache Line bits
011 = Contains data cache line size of 16 bytes
bit 9-7 DA<2:0>: Data-Cache Associativity bits
011 = Contains the 4-way set associativity for the data cache
bit 6-5 Unimplemented: Read as ‘0’
bit 4 PC: Performance Counter bit
1 = The processor core contains Performance Counters
bit 3 WR: Watch Register Presence bit
1 = No Watch registers are present
bit 2 CA: Code Compression Implemented bit
0 = No MIPS16e
®
present
bit 1 EP: EJTAG Present bit
1 = Core implements EJTAG
bit 0 FP: Floating Point Unit bit
1 = Floating Point Unit is present