Datasheet
2015 Microchip Technology Inc. Preliminary DS60001320B-page 51
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
3.7 M-Class Core Configuration
Register 3-1 through Register 3-4 show the default
configuration of the M-Class core, which is included on
PIC32MZ EF family devices.
REGISTER 3-1: CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
r-1 U-0 U-0 U-0 U-0 U-0 U-0 R-0
— — — — — — —ISP
23:16
R-0 R-0 R-1 R-0 U-0 R-1 R-0 R-0
DSP UDI SB MDU — MM<1:0> BM
15:8
R-0 R-0 R-0 R-0 R-0 R-1 R-0 R-0
BE AT<1:0> AR<2:0> MT<2:1>
7:0
R-1 U-0 U-0 U-0 U-0 R/W-0 R/W-1 R/W-0
MT<0> — — — — K0<2:0>
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: This bit is hardwired to ‘1’ to indicate the presence of the Config1 register.
bit 30-25 Unimplemented: Read as ‘0’
bit 24 ISP: Instruction Scratch Pad RAM bit
0 = Instruction Scratch Pad RAM is not implemented
bit 23 DSP: Data Scratch Pad RAM bit
0 = Data Scratch Pad RAM is not implemented
bit 22 UDI: User-defined bit
0 = CorExtend User-Defined Instructions are not implemented
bit 21 SB: SimpleBE bit
1 = Only Simple Byte Enables are allowed on the internal bus interface
bit 20 MDU: Multiply/Divide Unit bit
0 = Fast, high-performance MDU
bit 19 Unimplemented: Read as ‘0’
bit 18-17 MM<1:0>: Merge Mode bits
10 = Merging is allowed
bit 16 BM: Burst Mode bit
0 = Burst order is sequential
bit 15 BE: Endian Mode bit
0 = Little-endian
bit 14-13 AT<1:0>: Architecture Type bits
00 = MIPS32
bit 12-10 AR<2:0>: Architecture Revision Level bits
001 = MIPS32
Release 2
bit 9-7 MT<2:0>: MMU Type bits
001 = M-Class MPU Microprocessor core uses a TLB-based MMU
bit 6-3 Unimplemented: Read as ‘0’
bit 2-0 K0<2:0>: Kseg0 Coherency Algorithm bits
011 = Cacheable, non-coherent, write-back, write allocate
010 = Uncached
001 = Cacheable, non-coherent, write-through, write allocate
000 = Cacheable, non-coherent, write-through, no write allocate
All other values are not used and mapped to other values. 100, 101, and 110 are mapped to 010. 111 is
mapped to 010.