Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 49
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
The FPU implements a high-performance 7-stage
pipeline:
• Decode, register read and unpack (FR stage)
• Multiply tree - double pumped for double (M1
stage)
• Multiply complete (M2 stage)
• Addition first step (A1 stage)
• Addition second and final step (A2 stage)
• Packing to IEEE format (FP stage)
• Register writeback (FW stage)
The FPU implements a bypass mechanism that allows
the result of an operation to be forwarded directly to the
instruction that needs it without having to write the
result to the FPU register and then read it back.
Table 3-5 lists the Coprocessor 1 Registers for the
FPU.
TABLE 3-5: FPU (CP1) REGISTERS
3.2 Power Management
The processor core offers a number of power manage-
ment features, including low-power design, active power
management and power-down modes of operation. The
core is a static design that supports slowing or halting
the clocks, which reduces system power consumption
during Idle periods.
3.2.1 INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 33.0
“Power-Saving Features”.
3.2.2 LOCAL CLOCK GATING
The majority of the power consumed by the processor
core is in the clock tree and clocking registers. The
PIC32MZ family makes extensive use of local gated-
clocks to reduce this dynamic power consumption.
3.3 L1 Instruction and Data Caches
3.3.1 INSTRUCTION CACHE (I-CACHE)
The I-Cache is an on-core memory block of 16 Kbytes.
Because the I-Cache is virtually indexed, the virtual-to-
physical address translation occurs in parallel with the
cache access rather than having to wait for the physical
address translation. The tag holds 22 bits of physical
address, a valid bit, and a lock bit. The LRU
replacement bits are stored in a separate array.
The I-Cache block also contains and manages the
instruction line fill buffer. Besides accumulating data to
be written to the cache, instruction fetches that refer-
ence data in the line fill buffer are serviced either by a
bypass of that data, or data coming from the external
interface. The I-Cache control logic controls the bypass
function.
The processor core supports I-Cache locking. Cache
locking allows critical code or data segments to be
locked into the cache on a per-line basis, enabling the
system programmer to maximize the efficiency of the
system cache.
The cache locking function is always available on all
I-Cache entries. Entries can then be marked as
locked or unlocked on a per entry basis using the
CACHE instruction.
3.3.2 DATA CACHE (D-CACHE)
The D-Cache is an on-core memory block of 4 Kbytes.
This virtually indexed, physically tagged cache is pro
-
tected. Because the D-Cache is virtually indexed, the
virtual-to-physical address translation occurs in parallel
with the cache access. The tag holds 22 bits of physical
address, a valid bit, and a lock bit. There is an addi
-
tional array holding dirty bits and LRU replacement
algorithm bits for each set of the cache.
In addition to I-Cache locking, the processor core also
supports a D-Cache locking mechanism identical to the
I-Cache. Critical data segments are locked into the
cache on a per-line basis. The locked contents can be
updated on a store hit, but cannot be selected for
replacement on a cache miss.
The D-Cache locking function is always available on
all D-Cache entries. Entries can then be marked as
locked or unlocked on a per-entry basis using the
CACHE instruction.
3.3.3 ATTRIBUTES
The processor core I-Cache and D-Cache attributes
are listed in the Configuration registers (see
Register 3-1 through Register 3-4).
Register
Number
Register
Name
Function
0 FIR Floating Point implementation
register. Contains information
that identifies the FPU.
25 FCCR Floating Point condition codes
register.
26 FEXR Floating Point exceptions
register.
28 FENR Floating Point enables register.
31 FCSR Floating Point Control and
Status register.