Datasheet

2015 Microchip Technology Inc. Preliminary DS60001320B-page 489
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
00F0 C1FLTCON3
31:16 FLTEN15 MSEL15<1:0> FSEL15<4:0> FLTEN14 MSEL14<1:0> FSEL14<4:0> 0000
15:0 FLTEN13 MSEL13<1:0> FSEL13<4:0> FLTEN12 MSEL12<1:0> FSEL12<4:0> 0000
0100 C1FLTCON4
31:16 FLTEN19 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000
15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0> 0000
0110 C1FLTCON5
31:16 FLTEN23 MSEL23<1:0> FSEL23<4:0> FLTEN22 MSEL22<1:0> FSEL22<4:0> 0000
15:0 FLTEN21 MSEL21<1:0> FSEL21<4:0> FLTEN20 MSEL20<1:0> FSEL20<4:0> 0000
0120 C1FLTCON6
31:16 FLTEN27 MSEL27<1:0> FSEL27<4:0> FLTEN26 MSEL26<1:0> FSEL26<4:0> 0000
15:0 FLTEN25 MSEL25<1:0> FSEL25<4:0> FLTEN24 MSEL24<1:0> FSEL24<4:0> 0000
0130 C1FLTCON7
31:16 FLTEN31 MSEL31<1:0> FSEL31<4:0> FLTEN30 MSEL30<1:0> FSEL30<4:0> 0000
15:0 FLTEN29 MSEL29<1:0> FSEL29<4:0> FLTEN28 MSEL28<1:0> FSEL28<4:0> 0000
0140-
0330
C1RXFn
(n = 0-31)
31:16 SID<10:0> -— EXID EID<17:16>
xxxx
15:0 EID<15:0> xxxx
0340 C1FIFOBA
31:16
C1FIFOBA<31:0>
0000
15:0 0000
0350
C1FIFOCONn
(n = 0)
31:16 FSIZE<4:0> 0000
15:0 FRESET UINC DONLY TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000
0360
C1FIFOINTn
(n = 0)
31:16 TXNFULLIE TXHALFIE TXEMPTYIE RXOVFLIE RXFULLIE RXHALFIE
RXN
EMPTYIE
0000
15:0 TXNFULLIF TXHALFIF TXEMPTYIF RXOVFLIF RXFULLIF RXHALFIF
RXN
EMPTYIF
0000
0370
C1FIFOUAn
(n = 0)
31:16
C1FIFOUA<31:0>
0000
15:0 0000
0380
C1FIFOCIn
(n = 0)
31:16 0000
15:0 C1FIFOCI<4:0> 0000
0390-
0B40
C1FIFOCONn
C1FIFOINTn
C1FIFOUAn
C1FIFOCIn
(n = 1-31)
31:16 FSIZE<4:0> 0000
15:0 FRESET UINC DONLY TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000
31:16 TXNFULLIE TXHALFIE TXEMPTYIE RXOVFLIE RXFULLIE RXHALFIE
RXN
EMPTYIE
0000
15:0 TXNFULLIF TXHALFIF TXEMPTYIF RXOVFLIF RXFULLIF RXHALFIF
RXN
EMPTYIF
0000
31:16
C1FIFOUA<31:0>
0000
15:0 0000
31:16 0000
15:0 C1FIFOCI<4:0> 0000
TABLE 29-1: CAN1 REGISTER SUMMARY FOR PIC32MZXXXXECF AND PIC32MZXXXXECH DEVICES (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more
information.