Datasheet
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 488 Preliminary 2015 Microchip Technology Inc.
29.1 CAN Control Registers
Note: The ‘i’ shown in register names denotes
CAN1 or CAN2.
TABLE 29-1: CAN1 REGISTER SUMMARY FOR PIC32MZXXXXECF AND PIC32MZXXXXECH DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0000 C1CON
31:16 — — — — ABAT REQOP<2:0> OPMOD<2:0> CANCAP — — — — 0480
15:0 ON — SIDLE — CANBUSY — — — — — — DNCNT<4:0> 0000
0010 C1CFG
31:16 — — — — — — — — — WAKFIL — — — SEG2PH<2:0> 0000
15:0 SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> SJW<1:0> BRP<5:0> 0000
0020 C1INT
31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE — — — — — — — MODIE CTMRIE RBIE TBIE 0000
15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF — — — — — — — MODIF CTMRIF RBIF TBIF 0000
0030 C1VEC
31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — FILHIT<4:0> — ICODE<6:0> 0040
0040 C1TREC
31:16 — — — — — — — — — — TXBO TXBP RXBP TXWARN RXWARN EWARN 0000
15:0 TERRCNT<7:0> RERRCNT<7:0> 0000
0050 C1FSTAT
31:16 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000
15:0 FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 0000
0060 C1RXOVF
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
0070 C1TMR
31:16 CANTS<15:0> 0000
15:0 CANTSPRE<15:0> 0000
0080 C1RXM0
31:16 SID<10:0> -— MIDE — EID<17:16>
xxxx
15:0 EID<15:0> xxxx
0090 C1RXM1
31:16 SID<10:0> -— MIDE — EID<17:16>
xxxx
15:0 EID<15:0> xxxx
00A0 C1RXM2
31:16 SID<10:0> -— MIDE — EID<17:16>
xxxx
15:0 EID<15:0> xxxx
00B0 C1RXM3
31:16 SID<10:0> -— MIDE — EID<17:16>
xxxx
15:0 EID<15:0> xxxx
00C0 C1FLTCON0
31:16 FLTEN3 MSEL3<1:0> FSEL3<4:0> FLTEN2 MSEL2<1:0> FSEL2<4:0> 0000
15:0 FLTEN1 MSEL1<1:0> FSEL1<4:0> FLTEN0 MSEL0<1:0> FSEL0<4:0> 0000
00D0 C1FLTCON1
31:16 FLTEN7 MSEL7<1:0> FSEL7<4:0> FLTEN6 MSEL6<1:0> FSEL6<4:0> 0000
15:0 FLTEN5 MSEL5<1:0> FSEL5<4:0> FLTEN4 MSEL4<1:0> FSEL4<4:0> 0000
00E0 C1FLTCON2
31:16 FLTEN11 MSEL11<1:0> FSEL11<4:0> FLTEN10 MSEL10<1:0> FSEL10<4:0> 0000
15:0 FLTEN9 MSEL9<1:0> FSEL9<4:0> FLTEN8 MSEL8<1:0> FSEL8<4:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more
information.