Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 480 Preliminary  2015 Microchip Technology Inc.
REGISTER 28-30: ADCEISTAT1: ADC EARLY INTERRUPT STATUS REGISTER 1
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
EIRDY31
(1)
EIRDY30
(1)
EIRDY29
(1)
EIRDY28
(1)
EIRDY27
(1)
EIRDY26
(1)
EIRDY25
(1)
EIRDY24
(1)
23:16
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
EIRDY23
(1)
EIRDY22
(1)
EIRDY21
(1)
EIRDY20
(1)
EIRDY19
(1)
EIRDY18 EIRDY17 EIRDY16
15:8
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
EIRDY15 EIRDY14 EIRDY13 EIRDY12 EIRDY11 EIRDY10 EIRDY9 EIRDY8
7:0
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
EIRDY7 EIRDY6 EIRDY5 EIRDY4 EIRDY3 EIRDY2 EIRDY1 EIRDY0
Legend: HS = Hardware Set HC = Hardware Cleared
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 EIRDY31:EIRDY0: Early Interrupt for Corresponding Analog Input Ready bits
1 = This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be
generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs, this
bit will set as per the configuration of the ADCEIS<2:0> bits in the ADCxTIME register. For the shared
ADC module, this bit will be set as per the configuration of the ADCEIS<2:0> bits in the ADCCON2
register.
0 = Interrupts are disabled
Note 1: This bit is not available on 64-pin devices.