Datasheet
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 478 Preliminary 2015 Microchip Technology Inc.
REGISTER 28-27: ADCxTIME: DEDICATED ADCx TIMING REGISTER ‘x’ (‘x’ = 0 THROUGH 4)
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
— — — ADCEIS<2:0> SELRES<1:0>
23:16
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADCDIV<6:0>
15:8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SAMC<9:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SAMC<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 ADCEIS<2:0>: ADCx Early Interrupt Select bits
111 = The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
110 = The data ready interrupt is generated 7 ADC clocks prior to the end of conversion
•
•
•
001 = The data ready interrupt is generated 2 ADC clocks prior to the end of conversion
000 = The data ready interrupt is generated 1 ADC clock prior to the end of conversion
Note: All options are available when the selected resolution, specified by the SELRES<1:0> bits
(ADCxTIME<25:24>), is 12-bit or 10-bit. For a selected resolution of 8-bit, options from ‘000’
to ‘101’ are valid. For a selected resolution of 6-bit, options from ‘000’ to ‘011’ are valid.
bit 25-24 SELRES<1:0>: ADCx Resolution Select bits
11 = 12 bits
10 = 10 bits
01 = 8 bits
00 = 6 bits
bit 23 Unimplemented: Read as ‘0’
bit 22-16 ADCDIV<6:0>: ADCx Clock Divisor bits
These bits divide the ADC control clock with period T
Q to generate the clock for ADCx (TADx).
1111111 = 254 * TQ = TADx
•
•
•
0000011 = 6 * TQ = TADx
0000010 = 4 * T
Q = TADx
0000001 = 2 * T
Q = TADx
0000000 = Reserved
bit 15-10 Unimplemented: Read as ‘0’
bit 9-0 SAMC<9:0>: ADCx Sample Time bits
Where T
ADx = period of the ADC conversion clock for the dedicated ADC controlled by the ADCDIV<6:0>
bits.
1111111111 = 1025 T
ADx
•
•
•
0000000001 = 3 TADx
0000000000 = 2 T
ADx