Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 471
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 28-21: ADCCMPCONx: ADC DIGITAL COMPARATOR ‘x’ CONTROL REGISTER 
(‘x’ = 2 THROUGH 6)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
— — — AINID<4:0>
7:0
R/W-0 R/W-0 R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ENDCMP DCMPGIEN DCMPED IEBTWN IEHIHI IEHILO IELOHI IELOLO
Legend: HS = Hardware Set HC = Hardware Cleared
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-8 AINID<4:0>: Digital Comparator ‘x’ Analog Input Identification (ID) bits
When a digital comparator event occurs (DCMPED = 1), these bits identify the analog input being
monitored by the Digital Comparator.
Note: Only analog inputs <31:0> can be processed by the Digital Comparator module ‘x’ (‘x’ = 1-5).
11111 = AN31 is being monitored
11110 = AN30 is being monitored
•
•
•
00001 = AN1 is being monitored
00000 = AN0 is being monitored
bit 7 ENDCMP: Digital Comparator ‘x’ Enable bit
1 = Digital Comparator ‘x’ is enabled
0 = Digital Comparator ‘x’ is not enabled, and the DCMPED status bit (ADCCMPxCON<5>) is cleared
bit 6 DCMPGIEN: Digital Comparator ‘x’ Global Interrupt Enable bit
1 = A Digital Comparator ‘x’ interrupt is generated when the DCMPED status bit (ADCCMPxCON<5>) is set
0 = A Digital Comparator ‘x’ interrupt is disabled
bit 5 DCMPED: Digital Comparator ‘x’ “Output True” Event Status bit
The logical conditions under which the digital comparator gets “True” are defined by the IEBTWN, IEHIHI,
IEHILO, IELOHI and IELOLO bits.
Note: This bit is cleared by reading the AINID<5:0> bits (ADCCMP0CON<13:8>) or by disabling the
Digital Comparator module (by setting ENDCMP to ‘0’).
1 = Digital Comparator ‘x’ output true event has occurred (output of Comparator is ‘1’)
0 = Digital Comparator ‘x’ output is false (output of Comparator is ‘0’)
bit 4 IEBTWN: Between Low/High Digital Comparator ‘x’ Event bit
1 = Generate a digital comparator event when the DCMPLO<15:0> bits  DATA<31:0> bits
< DCMPHI<15:0> bits
0 = Do not generate a digital comparator event
bit 3 IEHIHI: High/High Digital Comparator ‘x’ Event bit
1 = Generate a Digital Comparator ‘x’ Event when the DCMPHI<15:0> bits  DATA<31:0> bits
0 = Do not generate an event
bit 2 IEHILO: High/Low Digital Comparator ‘x’ Event bit
1 = Generate a Digital Comparator ‘x’ Event when the DATA<31:0> bits
< DCMPHI<15:0> bits
0 = Do not generate an event