Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 47
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
12 Status Processor status and control.
IntCtl Interrupt control of vector spacing.
SRSCtl Shadow register set control.
SRSMap Shadow register mapping control.
View_IPL Allows the Priority Level to be read/written without
extracting or inserting that bit from/to the Status register.
SRSMAP2 Contains two 4-bit fields that provide the mapping from a vector number to the shadow
set number to use when servicing such an interrupt.
13 Cause Describes the cause of the last exception.
NestedExc Contains the error and exception level status bit values that existed prior to the current
exception.
View_RIPL Enables read access to the RIPL bit that is available in the Cause register.
14 EPC Program counter at last exception.
NestedEPC Contains the exception program counter that existed prior to the current exception.
15 PRID Processor identification and revision
Ebase Exception base address of exception vectors.
CDMMBase Common device memory map base.
16 Config Configuration register.
Config1 Configuration register 1.
Config2 Configuration register 2.
Config3 Configuration register 3.
Config4 Configuration register 4.
Config5 Configuration register 5.
Config7 Configuration register 7.
17 LLAddr Load link address (MPU only).
18 WatchLo Low-order watchpoint address (MPU only).
19 WatchHi High-order watchpoint address (MPU only).
20-22 Reserved Reserved in the PIC32 core.
23 Debug EJTAG debug register.
TraceControl EJTAG trace control.
TraceControl2 EJTAG trace control 2.
UserTraceData1 EJTAG user trace data 1 register.
TraceBPC EJTAG trace breakpoint register.
Debug2 Debug control/exception status 1.
24 DEPC Program counter at last debug exception.
UserTraceData2 EJTAG user trace data 2 register.
25 PerfCtl0 Performance counter 0 control.
PerfCnt0 Performance counter 0.
PerfCtl1 Performance counter 1 control.
PerfCnt1 Performance counter 1.
26 ErrCtl Software test enable of way-select and data RAM arrays for I-Cache and D-Cache
(MPU only).
27 Reserved Reserved in the PIC32 core.
28 TagLo/DataLo Low-order portion of cache tag interface (MPU only).
29 Reserved Reserved in the PIC32 core.
30 ErrorEPC Program counter at last error exception.
31 DeSave Debug exception save.
TABLE 3-3: COPROCESSOR 0 REGISTERS (CONTINUED)
Register
Number
Register
Name
Function