Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 469
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 28-20: ADCCMPCON1: ADC DIGITAL COMPARATOR 1 CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
CVDDATA<15:8>
23:16
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
CVDDATA<7:0>
15:8
U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
— — AINID<5:0>
7:0
R/W-0 R/W-0 R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ENDCMP DCMPGIEN DCMPED IEBTWN IEHIHI IEHILO IELOHI IELOLO
Legend: HS = Hardware Set HC = Hardware Cleared
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 CVDDATA<15:0>: CVD Data Status bits
In CVD mode, these bits obtain the CVD differential output data (subtraction of CVD positive and negative
measurement), whenever a Digital Comparator interrupt is generated. The value in these bits is compliant
with the FRACT bit (ADCCON1<23>) and is always signed.
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 AINID<5:0>: Digital Comparator 0 Analog Input Identification (ID) bits
When a digital comparator event occurs (DCMPED = 1), these bits identify the analog input being
monitored by Digital Comparator 0.
Note: In normal ADC mode, only analog inputs <31:0> can be processed by the Digital Comparator 0.
The Digital Comparator 0 also supports the CVD mode, in which all Class 2 and Class 3 analog
inputs may be stored in the AINID<5:0> bits.
111111 = Reserved
•
•
•
101101 = Reserved
101100 = AN44 is being monitored
101011 = AN43 is being monitored
•
•
•
000001 = AN1 is being monitored
000000 = AN0 is being monitored
bit 7 ENDCMP: Digital Comparator 0 Enable bit
1 = Digital Comparator 0 is enabled
0 = Digital Comparator 0 is not enabled, and the DCMPED status bit (ADCCMP0CON<5>) is cleared
bit 6 DCMPGIEN: Digital Comparator 0 Global Interrupt Enable bit
1 = A Digital Comparator 0 interrupt is generated when the DCMPED status bit (ADCCMP0CON<5>) is set
0 = A Digital Comparator 0 interrupt is disabled
bit 5 DCMPED: Digital Comparator 0 “Output True” Event Status bit
The logical conditions under which the digital comparator gets “True” are defined by the IEBTWN, IEHIHI,
IEHILO, IELOHI, and IELOLO bits.
Note: This bit is cleared by reading the AINID<5:0> bits or by disabling the Digital Comparator module
(by setting ENDCMP to ‘0’).
1 = Digital Comparator 0 output true event has occurred (output of Comparator is ‘1’)
0 = Digital Comparator 0 output is false (output of comparator is ‘0’)
bit 4 IEBTWN: Between Low/High Digital Comparator 0 Event bit
1 = Generate a digital comparator event when DCMPLO<15:0>  DATA<31:0>
< DCMPHI<15:0>
0 = Do not generate a digital comparator event