Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 46 Preliminary  2015 Microchip Technology Inc.
The MIPS architecture defines that the result of a
multiply or divide operation be placed in one of four
pairs of HI and LO registers. Using the Move-From-HI
(MFHI) and Move-From-LO (MFLO) instructions, these
values can be transferred to the General Purpose
Register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruc
-
tion, MUL, which places the least significant results in
the primary register file instead of the HI/LO register
pair. By avoiding the explicit MFLO instruction
required when using the LO register, and by support
-
ing multiple destination registers, the throughput of
multiply-intensive operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
The MDU also implements various shift instructions
operating on the HI/LO register and multiply instruc
-
tions as defined in the DSP ASE. The MDU supports all
of the data types required for this purpose and includes
three extra HI/LO registers as defined by the ASE.
Table 3-2 lists the latencies and repeat rates for the
DSP multiply and dot-product operations. The approxi-
mate latencies and repeat rates are listed in terms of
pipeline clocks.
TABLE 3-2: DSP-RELATED LATENCIES
AND REPEAT RATES
3.1.3 SYSTEM CONTROL 
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation and cache proto
-
cols, the exception control system, the processor’s
diagnostics capability, the operating modes (Kernel,
User and Debug) and whether interrupts are enabled or
disabled. Configuration information, such as cache
size and set associativity, and the presence of options
like microMIPS is also available by accessing the CP0
registers, listed in
Table 3-3.
Op code Latency
Repeat
Rate
Multiply and dot-product without
saturation after accumulation
5 1
Multiply and dot-product with
saturation after accumulation
5 1
Multiply without accumulation 5 1
TABLE 3-3: COPROCESSOR 0 REGISTERS
Register
Number
Register
Name
Function
0 Index Index into the TLB array (MPU only).
1 Random Randomly generated index into the TLB array (MPU only).
2 EntryLo0 Low-order portion of the TLB entry for even-numbered virtual pages (MPU only).
3 EntryLo1 Low-order portion of the TLB entry for odd-numbered virtual pages (MPU only).
4 Context/
UserLocal
Pointer to the page table entry in memory (MPU only).
User information that can be written by privileged software and read via the RDHWR
instruction.
5 PageMask/
PageGrain
PageMask controls the variable page sizes in TLB entries. PageGrain enables support
of 1 KB pages in the TLB (MPU only).
6 Wired Controls the number of fixed (i.e., wired) TLB entries (MPU only).
7 HWREna Enables access via the RDHWR instruction to selected hardware registers in 
Non-privileged mode.
8 BadVAddr Reports the address for the most recent address-related exception.
BadInstr Reports the instruction that caused the most recent exception.
BadInstrP Reports the branch instruction if a delay slot caused the most recent exception.
9 Count Processor cycle count.
10 EntryHi High-order portion of the TLB entry (MPU only).
11 Compare Core timer interrupt control.