Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 45
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
3.1 Architecture Overview
The MIPS32 M-Class Microprocessor core in PIC32MZ
EF family devices contains several logic blocks working
together in parallel, providing an efficient high-perfor
-
mance computing engine. The following blocks are
included with the core:
• Execution unit
• General Purpose Register (GPR)
• Multiply/Divide Unit (MDU)
• System control coprocessor (CP0)
• Floating Point Unit (FPU)
• Memory Management Unit (MMU)
• Instruction/Data cache controllers
• Power Management
• Instructions and data caches
• microMIPS support
• Enhanced JTAG (EJTAG) controller
3.1.1 EXECUTION UNIT
The processor core execution unit implements a load/
store architecture with single-cycle ALU operations
(logical, shift, add, subtract) and an autonomous multi
-
ply/divide unit. The core contains thirty-two 32-bit Gen-
eral Purpose Registers (GPRs) used for integer
operations and address calculation. Seven additional
register file shadow sets (containing thirty-two regis-
ters) are added to minimize context switching overhead
during interrupt/exception processing. The register file
consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Trap condition comparator
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
• Leading Zero/One detect unit for implementing
the CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing arithmetic
and bitwise logical operations
• Shifter and store aligner
• DSP ALU and logic block for performing DSP
instructions, such as arithmetic/shift/compare
operations
3.1.2 MULTIPLY/DIVIDE UNIT (MDU)
The processor core includes a Multiply/Divide Unit
(MDU) that contains a separate pipeline for multiply
and divide operations, and DSP ASE multiply instruc-
tions. This pipeline operates in parallel with the Integer
Unit (IU) pipeline and does not stall when the IU pipe
-
line stalls. This allows MDU operations to be partially
masked by system stalls and/or other integer unit
instructions.
The high-performance MDU consists of a 32x32 booth
recoded multiplier, four pairs of result/accumulation
registers (HI and LO), a divide state machine, and the
necessary multiplexers and control logic. The first num
-
ber shown (‘32’ of 32x32) represents the rs operand.
The second number (‘32’ of 32x32) represents the rt
operand.
The MDU supports execution of one multiply or
multiply-accumulate operation every clock cycle.
Divide operations are implemented with a simple 1-bit-
per-clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) oper
-
and. If rs is 8 bits wide, 23 iterations are skipped. For
a 16-bit wide rs, 15 iterations are skipped and for a
24-bit wide rs, 7 iterations are skipped. Any attempt to
issue a subsequent MDU instruction while a divide is
still active causes an IU pipeline stall until the divide
operation has completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (num-
ber of cycles until a result is available) for the processor
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
TABLE 3-1: MIPS32
®
M-CLASS MICROPROCESSOR CORE HIGH-PERFORMANCE INTEGER
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU (HI/LO destination)
16 bits 5 1
32 bits 5 1
MUL (GPR destination) 16 bits 5 1
32 bits 5 1
DIV/DIVU 8 bits 12/14 12/14
16 bits 20/22 20/22
24 bits 28/30 28/30
32 bits 36/38 36/38