Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family

DS60001320B-page 446 Preliminary  2015 Microchip Technology Inc.

bit 6 GSWTRG: Global Software Trigger bit

1 = Trigger conversion for ADC inputs that have selected the GSWTRG bit as the trigger signal, either

through the associated TRGSRC<4:0> bits in the ADCTRGx registers or through the STRGSRC<4:0>

bits in the ADCCON1 register

0 = Do not trigger an analog-to-digital conversion

Note: This bit is automatically cleared in the next ADC clock cycle.

bit 5-0 ADINSEL<5:0>: Analog Input Select bits

These bits select the analog input to be converted when the RQCNVRT bit is set. As a general rule:

111111 = Reserved

•

101101 = Reserved

101100 = MAX_AN_INPUT + 2 = IV

TEMP

101011 = MAX_AN_INPUT + 1 = IVREF

101010 = MAX_AN_INPUT = AN[MAX_AN_INPUT]

•

000001 = AN1

000000 = AN0

Note 1: The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the

bit is cleared. Also, usage of the SAMP bit will cause settings of SAMC<9:0> bits (ADCCON2<25:16>) to

be ignored.

2: The SAMP bit only connects Class 2 and Class 3 analog inputs to the shared ADC, ADC7. All Class 1

analog inputs are not affected by the SAMP bit.

3: The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit

and only after setting the RQCNVRT bit to start the analog-to-digital conversion.

4: Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx<4:0> bits

and STRGSRC<4:0> bits should be set to ‘00000’ to disable all external hardware triggers and prevent

them from interfering with the software-controlled sampling command signal SAMP and with the

software-controlled trigger RQCNVRT.