Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 445
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
bit 18 DIGEN2: ADC2 Digital Enable bit
1 = ADC2 is digital enabled
0 = ADC2 is digital disabled
bit 17 DIGEN1: ADC1 Digital Enable bit
1 = ADC1 is digital enabled
0 = ADC1 is digital disabled
bit 16 DIGEN0: ADC0 Digital Enable bit
1 = ADC0 is digital enabled
0 = ADC0 is digital disabled
bit 15-13 VREFSEL<2:0>: Voltage Reference (V
REF) Input Selection bits
bit 12 TRGSUSP: Trigger Suspend bit
1 = Triggers are blocked from starting a new analog-to-digital conversion, but the ADC module is not disabled
0 = Triggers are not blocked
bit 11 UPDIEN: Update Ready Interrupt Enable bit
1 = Interrupt will be generated when the UPDRDY bit is set by hardware
0 = No interrupt is generated
bit 10 UPDRDY: ADC Update Ready Status bit
1 = ADC SFRs can be updated
0 = ADC SFRs cannot be updated
Note: This bit is only active while the TRGSUSP bit is set and there are no more running conversions of
any ADC modules.
bit 9 SAMP: Class 2 and Class 3 Analog Input Sampling Enable bit
(1,2,3,4)
1 = The ADC S&H amplifier is sampling
0 = The ADC S&H amplifier is holding
bit 8 RQCNVRT: Individual ADC Input Conversion Request bit
This bit and its associated ADINSEL<5:0> bits enable the user to individually request an analog-to-digital
conversion of an analog input through software.
1 = Trigger the conversion of the selected ADC input as specified by the ADINSEL<5:0> bits
0 = Do not trigger the conversion
Note: This bit is automatically cleared in the next ADC clock cycle.
bit 7 GLSWTRG: Global Level Software Trigger bit
1 = Trigger conversion for ADC inputs that have selected the GLSWTRG bit as the trigger signal, either
through the associated TRGSRC<4:0> bits in the ADCTRGx registers or through the STRGSRC<4:0>
bits in the ADCCON1 register
0 = Do not trigger an analog-to-digital conversion
REGISTER 28-3: ADCCON3: ADC CONTROL REGISTER 3 (CONTINUED)
Note 1: The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the
bit is cleared. Also, usage of the SAMP bit will cause settings of SAMC<9:0> bits (ADCCON2<25:16>) to
be ignored.
2: The SAMP bit only connects Class 2 and Class 3 analog inputs to the shared ADC, ADC7. All Class 1
analog inputs are not affected by the SAMP bit.
3: The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit
and only after setting the RQCNVRT bit to start the analog-to-digital conversion.
4: Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx<4:0> bits
and STRGSRC<4:0> bits should be set to ‘00000’ to disable all external hardware triggers and prevent
them from interfering with the software-controlled sampling command signal SAMP and with the
software-controlled trigger RQCNVRT.
VREFSEL<2:0> ADREF+ADREF-
1xx Reserved; do not use
011 External V
REFH External VREFL
010 AVDD External VREFL
001 External VREFH AVss
000 AV
DD AVss