Datasheet
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 444 Preliminary 2015 Microchip Technology Inc.
REGISTER 28-3: ADCCON3: ADC CONTROL REGISTER 3
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCSEL<1:0> CONCLKDIV<5:0>
23:16
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIGEN7 — — DIGEN4 DIGEN3 DIGEN2 DIGEN1 DIGEN0
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC R/W-0 R-0, HS, HC
VREFSEL<2:0> TRGSUSP UPDIEN UPDRDY SAMP
(1,2,3,4)
RQCNVRT
7:0
R/W-0 R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GLSWTRG GSWTRG ADINSEL<5:0>
Legend: HC = Hardware Set HS = Hardware Cleared
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-30 ADCSEL<1:0>: Analog-to-Digital Clock Source (TCLK) bits
11 = FRC
10 = REFCLK3
01 = System Clock (Tcy)
00 = PBCLK3
bit 29-24 CONCLKDIV<5:0>: Analog-to-Digital Control Clock (T
Q) Divider bits
111111 = 64 * TCLK = TQ
•
•
•
000011 = 4 * TCLK = TQ
000010 = 3 * TCLK = TQ
000001 = 2 * TCLK = TQ
000000 = TCLK = TQ
bit 23 DIGEN7: Shared ADC (ADC7) Digital Enable bit
1 = ADC7 is digital enabled
0 = ADC7 is digital disabled
bit 22-21 Unimplemented: Read as ‘0’
bit 20 DIGEN4: ADC4 Digital Enable bit
1 = ADC4 is digital enabled
0 = ADC4 is digital disabled
bit 19 DIGEN3: ADC3 Digital Enable bit
1 = ADC3 is digital enabled
0 = ADC3 is digital disabled
Note 1: The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the
bit is cleared. Also, usage of the SAMP bit will cause settings of SAMC<9:0> bits (ADCCON2<25:16>) to
be ignored.
2: The SAMP bit only connects Class 2 and Class 3 analog inputs to the shared ADC, ADC7. All Class 1
analog inputs are not affected by the SAMP bit.
3: The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit
and only after setting the RQCNVRT bit to start the analog-to-digital conversion.
4: Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx<4:0> bits
and STRGSRC<4:0> bits should be set to ‘00000’ to disable all external hardware triggers and prevent
them from interfering with the software-controlled sampling command signal SAMP and with the
software-controlled trigger RQCNVRT.