Datasheet
2015 Microchip Technology Inc. Preliminary DS60001320B-page 443
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
bit 14 REFFLTIEN: Band Gap/VREF Voltage Fault Interrupt Enable bit
1 = Interrupt will be generated when the REFFLT bit is set
0 = No interrupt is generated when the REFFLT bit is set
bit 13 EOSIEN: End of Scan Interrupt Enable bit
1 = Interrupt will be generated when EOSRDY bit is set
0 = No interrupt is generated when the EOSRDY bit is set
bit 12 ADCEIOVR: Early Interrupt Request Override bit
1 = Early interrupt generation is not overridden and interrupt generation is controlled by the ADCEIEN1
and ADCEIEN2 registers
0 = Early interrupt generation is overridden and interrupt generation is controlled by the ADCGIRQEN1
and ADCGIRQEN2 registers
bit 11 Unimplemented: Read as ‘0’
bit 10-8 ADCEIS<2:0>: Shared ADC (ADC7) Early Interrupt Select bits
These bits select the number of clocks (T
AD
7)
prior to the arrival of valid data that the associated interrupt
is generated.
111 = The data ready interrupt is generated 8 ADC clocks prior to end of conversion
110 = The data ready interrupt is generated 7 ADC clocks prior to end of conversion
•
•
•
001 = The data ready interrupt is generated 2 ADC module clocks prior to end of conversion
000 = The data ready interrupt is generated 1 ADC module clock prior to end of conversion
Note: All options are available when the selected resolution, set by the SELRES<1:0> bits
(ADCCON1<22:21>), is 12-bit or 10-bit. For a selected resolution of 8-bit, options from ‘000’ to
‘101’ are valid. For a selected resolution of 6-bit, options from ‘000’ to ‘011’ are valid.
bit 7 Unimplemented: Read as ‘0’
bit 6-0 ADCDIV<6:0>: Shared ADC (ADC7) Clock Divider bits
1111111 = 254 * T
Q = TAD
7
•
•
•
0000011 = 6 * TQ = TAD
7
0000010 = 4 * TQ = TAD
7
0000001 = 2 * TQ = TAD
7
0000000 = Reserved
The ADCDIV<6:0> bits divide the ADC control clock (T
Q) to generate the clock for the Shared ADC, ADC7
(T
AD
7
).
REGISTER 28-2: ADCCON2: ADC CONTROL REGISTER 2 (CONTINUED)