Datasheet
2015 Microchip Technology Inc. Preliminary DS60001320B-page 43
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
3.0 CPU
The MIPS32
®
M-Class Core is the heart of the
PIC32MZ EF family device processor. The CPU
fetches instructions, decodes each instruction, fetches
source operands, executes each instruction and writes
the results of instruction execution to the proper
destinations.
Key features include:
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32 Enhanced Architecture (Release 5):
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency for
interrupt handlers
- Bit field manipulation instructions
- Virtual memory support
• microMIPS™ compatible instruction set:
- Improves code size density over MIPS32, while
maintaining MIPS32 performance.
- Supports all MIPS32 instructions (except branch-
likely instructions)
- Fifteen additional 32-bit instructions and 39 16-bit
instructions corresponding to commonly-used
MIPS32 instructions
- Stack pointer implicit in instruction
- MIPS32 assembly and ABI compatible
• MMU with Translation Lookaside Buffer (TLB)
mechanism:
- 16 dual-entry fully associative Joint TLB
- 4-entry fully associative Instruction and Data TLB
- 4 KB pages
• Separate L1 data and instruction caches:
- 16 KB 4-way Instruction Cache (I-Cache)
- 4 KB 4-way Data Cache (D-Cache)
• Autonomous Multiply/Divide Unit (MDU):
- Maximum issue rate of one 32x32 multiply per clock
- Early-in iterative divide. Minimum 12 and
maximum 38 clock latency (dividend (rs) sign
extension-dependent)
• Power Control:
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT instruction)
- Extensive use of local gated clocks
• EJTAG Debug and Instruction Trace:
- Support for single stepping
- Virtual instruction and data address/value
breakpoints
- Hardware breakpoint supports both address
match and address range triggering.
- Eight instruction and four data complex
breakpoints
• iFlowtrace
®
version 2.0 support:
- Real-time instruction program counter
- Special events trace capability
- Two performance counters with 34 user-
selectable countable events
- Disabled if the processor enters Debug mode
- Program Counter sampling
• Four Watch registers:
- Instruction, Data Read, Data Write options
- Address match masking options
• DSP ASE Extension:
- Native fractional format data type operations
- Register Single Instruction Multiple Data (SIMD)
operations (add, subtract, multiply, shift)
- GPR-based shift
- Bit manipulation
- Compare-Pick
- DSP Control Access
- Indexed-Load
-Branch
- Multiplication of complex operands
- Variable bit insertion and extraction
- Virtual circular buffers
- Arithmetic saturation and overflow handling
- Zero-cycle overhead saturation and rounding
operations
• Floating Point Unit (FPU):
- 1985 IEEE-754 compliant Floating Point Unit
- Supports single and double precision datatypes
- 2008 IEEE-754 compatibility control of NaN
handling and Abs/Neg instructions
- Runs at 1:1 core/FPU clock ratio
Note 1: This data sheet summarizes the fea-
tures of the PIC32MZ EF family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 50. “CPU for
Devices with MIPS32
®
microAptiv™
and M-Class Cores” (DS60001192) of
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web
site (www.microchip.com/PIC32).
2: The Series 5 Warrior M-class CPU core
resources are available at:
www.imgtec.com.