Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 411
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 26-7: CEINTEN: CRYPTO ENGINE INTERRUPT ENABLE REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — AREIE PKTIE BDPIE PENDIE
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3 AREIE: Access Response Error Interrupt Enable bit
1 = Access response error interrupts are enabled
0 = Access response error interrupts are not enabled
bit 2 PKTIE: DMA Packet Completion Interrupt Enable bit
1 = DMA packet completion interrupts are enabled
0 = DMA packet completion interrupts are not enabled
bit 1 BDPIE: DMA Buffer Descriptor Processor Interrupt Enable bit
1 = BDP interrupts are enabled
0 = BDP interrupts are not enabled
bit 0 PENDIE: Master Interrupt Enable bit
(1)
1 = Crypto Engine interrupts are enabled
0 = Crypto Engine interrupts are not enabled
Note 1: The PENDIE bit is a Global enable bit and must be enabled together with the other interrupts desired.