Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 372 Preliminary 2015 Microchip Technology Inc.
23.1 PMP Control Registers
TABLE 23-1: PARALLEL MASTER PORT REGISTER MAP
Virtual Address
(BF82_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
E000 PMCON
31:16 RDSTART DUALBUF 0000
15:0 ON SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN CSF<1:0> ALP CS2P CS1P WRSP RDSP 0000
E010 PMMODE
31:16 0000
15:0 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000
E020 PMADDR
31:16 0000
15:0
CS2 CS1
ADDR<13:0>
0000
ADDR15 ADDR14
0000
E030 PMDOUT
31:16 0000
15:0 DATAOUT<15:0> 0000
E040 PMDIN
31:16 0000
15:0 DATAIN<15:0> 0000
E050 PMAEN
31:16 0000
15:0
PTEN<15:0>
0000
E060 PMSTAT
31:16 0000
15:0 IBF IBOV IB3F IB2F IB1F IB0F OBE OBUF OB3E OB2E OB1E OB0E 008F
E070 PMWADDR
31:16 0000
15:0
WCS2 WCS1
0000
WADDR15 WADDR14
WADDR<13:0>
0000
E080 PMRADDR
31:16 0000
15:0
RCS2 RCS1
0000
RADDR15 RADDR14
RADDR<13:0>
0000
E090 PMRDIN
31:16 31:16 0000
15:0 15:0
RDATAIN<15:0>
0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for
more information.