Datasheet

2015 Microchip Technology Inc. Preliminary DS60001320B-page 365
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2600 U4MODE
(1)
31:16
15:0
0000
ON SIDL IREN RTSMD UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
2610 U4STA
(1)
31:16 ADM_EN ADDR<7:0> 0000
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
2620 U4TXREG
31:16 0000
15:0 TX8 Transmit Register 0000
2630 U4RXREG
31:16 0000
15:0 RX8 Receive Register 0000
2640 U4BRG
(1)
31:16 0000
15:0 Baud Rate Generator Prescaler 0000
2800 U5MODE
(1)
31:16
15:0
0000
ON SIDL IREN RTSMD UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
2810 U5STA
(1)
31:16 ADM_EN ADDR<7:0> 0000
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
2820 U5TXREG
31:16 0000
15:0 TX8 Transmit Register 0000
2830 U5RXREG
31:16 0000
15:0 RX8 Receive Register 0000
2840 U5BRG
(1)
31:16 0000
15:0 Baud Rate Generator Prescaler 0000
2A00 U6MODE
(1)
31:16
15:0
0000
ON SIDL IREN RTSMD UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
2A10 U6STA
(1)
31:16 ADM_EN ADDR<7:0> 0000
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
2A20 U6TXREG
31:16 0000
15:0 TX8 Transmit Register 0000
2A30 U6RXREG
31:16 0000
15:0 RX8 Receive Register 0000
2A40 U6BRG
(1)
31:16 0000
15:0 Baud Rate Generator Prescaler 0000
TABLE 22-1: UART1 THROUGH UART6 REGISTER MAP (CONTINUED)
Virtual Address
(BF82_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers for more informa-
tion.