Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 359
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 21-1: I2CXCON: I
2
C CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
15:8
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
ON — SIDL SCKREL STRICT A10M DISSLW SMEN
7:0
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
Legend: HC = Cleared in Hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-23 Unimplemented: Read as ‘0’
bit 22 PCIE: Stop Condition Interrupt Enable bit (I
2
C Slave mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
bit 21 SCIE: Start Condition Interrupt Enable bit (I
2
C Slave mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
bit 20 BOEN: Buffer Overwrite Enable bit (I
2
C Slave mode only)
1 = I2CxRCV is updated and ACK
is generated for a received address/data byte, ignoring the state of the
I2COV bit (I2CxSTAT<6>)only if the RBF bit (I2CxSTAT<2>) = 0
0 = I2CxRCV is only updated when the I2COV bit (I2CxSTAT<6>) is clear
bit 19 SDAHT: SDA Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 18 SBCDE: Slave Mode Bus Collision Detect Enable bit (I
2
C Slave mode only)
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 18 AHEN: Address Hold Enable bit (Slave mode only)
1 = Following the 8th falling edge of SCL for a matching received address byte; SCKREL bit will be cleared
and the SCL will be held low.
0 = Address holding is disabled
bit 16 DHEN: Data Hold Enable bit (I
2
C Slave mode only)
1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the SCKREL bit
and SCL is held low
0 = Data holding is disabled
bit 15 ON: I
2
C Enable bit
1 = Enables the I
2
C module and configures the SDA and SCL pins as serial port pins
0 = Disables the I
2
C module; all I
2
C pins are controlled by PORT functions
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode