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ManualsBrandsMicrochip ManualsEmbedded Processors & ControllersMicrocontroller 32 Bit TQFP-64
351352353354355356357358359360
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 352 Preliminary 2015 Microchip Technology Inc.
REGISTER 20-25: SQI1XCON3: SQI XIP CONTROL REGISTER 3
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — INIT1SCHECK INIT1COUNT<1:0> INIT1TYPE<1:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INIT1CMD3<7:0>
(1)
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INIT1CMD2<7:0>
(1)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INIT1CMD1<7:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28 INIT1SCHECK: Flash Initialization 1 Command Status Check bit
1 = Check the status after executing the INIT1 command
0 = Do not check the status
bit 27-26 INIT1COUNT<1:0>: Flash Initialization 1 Command Count bits
11 = INIT1CMD1, INIT1CMD2, and INIT1CMD3 are sent
10 = INIT1CMD1 and INIT1CMD2 are sent, but INIT1CMD3 is still pending
01 = INIT1CMD1 is sent, but INIT1CMD2 and INIT1CMD3 are still pending
00 = No commands are sent
bit 25-24 INIT1TYPE<1:0>: Flash Initialization 1 Command Type bits
11 = Reserved
10 = INIT1 commands are sent in Quad Lane mode
01 = INIT1 commands are sent in Dual Lane mode
00 = INIT1 commands are sent in Single Lane mode
bit 24-16 INIT1CMD3<7:0>: Flash Initialization Command 3 bits
(1)
Third command of the Flash initialization.
bit 15-8 INIT1CMD2<7:0>: Flash Initialization Command 2 bits
(1)
Second command of the Flash initialization.
bit 7-0 INIT1CMD1<7:0>: Flash Initialization Command 1 bits
(1)
First command of the Flash initialization.
Note 1: INIT1CMD1 can be WEN and INIT1CMD2 can be SECTOR UNPROTECT.
Note: Some Flash devices require write enable and sector unprotect commands before write/read operations and
this register is useful in working with those Flash types (XIP mode only)