Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 348 Preliminary  2015 Microchip Technology Inc.
REGISTER 20-20: SQI1BDRXDSTAT: SQI BUFFER DESCRIPTOR DMA RECEIVE STATUS
REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 R-x R-x R-x R-x U-0
— — — RXSTATE<3:0> —
23:16
U-0 U-0 U-0 R-x R-x R-x R-x R-x
— — — RXBUFCNT<4:0>
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R-x R-x R-x R-x R-x R-x R-x R-x
RXCURBUFLEN<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-25 RXSTATE<3:0>: Current DMA Receive State Status bits
These bits provide information on the current DMA receive states.
bit 24-21 Unimplemented: Read as ‘0’
bit 20-16 RXBUFCNT<4:0>: DMA Buffer Byte Count Status bits
These bits provide information on the internal FIFO space.
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 RXCURBUFLEN<7:0>: Current DMA Receive Buffer Length Status bits
These bits provide the length of the current DMA receive buffer.
REGISTER 20-21: SQI1THR: SQI THRESHOLD CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— THRES<6:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-7 Unimplemented: Read as ‘0’
bit 6-0 THRES<6:0>: SQI Control Threshold Value bits
The SQI control threshold interrupt is asserted when the amount of space indicated by THRES<6:0> is
available in the SQI control buffer.