Datasheet
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 346 Preliminary 2015 Microchip Technology Inc.
REGISTER 20-16: SQI1BDBASEADD: SQI BUFFER DESCRIPTOR BASE ADDRESS REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BDADDR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BDADDR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BDADDR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BDADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 BDADDR<31:0>: DMA Base Address bits
These bits contain the physical address of the root buffer descriptor. This register should be updated only
when the DMA is idle.
REGISTER 20-17: SQI1BDSTAT: SQI BUFFER DESCRIPTOR STATUS REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 R-x R-x R-x R-x R-x R-x
— — BDSTATE<3:0> DMASTART DMAACTV
15:8
R-x R-x R-x R-x R-x R-x R-x R-x
BDCON<15:8>
7:0
R-x R-x R-x R-x R-x R-x R-x R-x
BDCON<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-22 Unimplemented: Read as ‘0’
bit 21-18 BDSTATE<3:0>: DMA Buffer Descriptor Processor State Status bits
These bits return the current state of the buffer descriptor processor:
5 = Fetched buffer descriptor is disabled
4 = Descriptor is done
3 = Data phase
2 = Buffer descriptor is loading
1 = Descriptor fetch request is pending
0 = Idle
bit 17 DMASTART: DMA Buffer Descriptor Processor Start Status bit
1 = DMA has started
0 = DMA has not started
bit 16 DMAACTV: DMA Buffer Descriptor Processor Active Status bit
1 = Buffer Descriptor Processor is active
0 = Buffer Descriptor Processor is idle
bit 15-0 BDCON<15:0>: DMA Buffer Descriptor Control Word bits
These bits contain the current buffer descriptor control word.