Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 338 Preliminary  2015 Microchip Technology Inc.
REGISTER 20-7: SQI1INTTHR: SQI INTERRUPT THRESHOLD REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —TXINTTHR<4:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RXINTTHR<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-8 TXINTTHR<4:0>: Transmit Interrupt Threshold bits
A transmit interrupt is set when the transmit FIFO has more space than the set number of bytes. For 16-bit
mode, the value should be a multiple of 2.
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RXINTTHR<4:0>: Receive Interrupt Threshold bits
A receive interrupt is set when the receive FIFO count is larger than or equal to the set number of bytes. For
16-bit mode, the value should be multiple of 2.