Datasheet
2015 Microchip Technology Inc. Preliminary DS60001320B-page 335
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 20-4: SQI1CON: SQI CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 r-0 R/W-0
— — — — — — — SCHECK
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DDRMODE DASSERT DEVSEL<1:0> LANEMODE<1:0> CMDINIT<1:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXRXCOUNT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXRXCOUNT<7:0>
Legend: r = Reserved
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25 Reserved: Must be programmed as ‘0’
bit 24 SCHECK: Flash Status Check bit
1 = Check the status of the Flash
0 = Do not check the status of the Flash
bit 23 DDRMODE: Double Data Rate Mode bit
1 = Set the SQI transfers to DDR mode
0 = Set the SQI transfers to SDR mode
bit 22 DASSERT: Chip Select Assert bit
1 = Chip Select is deasserted after transmission or reception of the specified number of bytes
0 = Chip Select is not deasserted after transmission or reception of the specified number of bytes
bit 21-20 DEVSEL<1:0>: SQI Device Select bits
11 = Reserved
10 = Reserved
01 = Select Device 1
00 = Select Device 0
bit 19-18 LANEMODE<1:0>: SQI Lane Mode Select bits
11 = Reserved
10 = Quad Lane mode
01 = Dual Lane mode
00 = Single Lane mode
bit 17-16 CMDINIT<1:0>: Command Initiation Mode Select bits
If it is Transmit, commands are initiated based on a write to the transmit register or the contents of TX
FIFO. If CMDINIT is Receive, commands are initiated based on reads to the read register or RX FIFO
availability.
11 = Reserved
10 = Receive
01 = Transmit
00 = Idle
bit 15-0 TXRXCOUNT<15:0>: Transmit/Receive Count bits
These bits specify the total number of bytes to transmit or received (based on CMDINIT)