Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family

DS60001320B-page 334 Preliminary  2015 Microchip Technology Inc.

bit 12 BURSTEN: Burst Configuration bit

(1)

1 = Burst is enabled

0 = Burst is not enabled

bit 11 Reserved: Must be programmed as ‘0’

bit 10 HOLD: Hold bit

In Single Lane or Dual Lane mode, this bit is used to drive the SQID3 pin, which can be used for devices

with a HOLD input pin. The meaning of the values for this bit will depend on the device to which SQID3 is

connected.

bit 9 WP: Write Protect bit

In Single Lane or Dual Lane mode, this bit is used to drive the SQID2 pin, which can be used with devices

with a write-protect pin. The meaning of the values for this bit will depend on the device to which SQID2 is

connected.

bit 8-6 Unimplemented: Read as ‘0’

bit 5 LSBF: Data Format Select bit

1 = LSB is sent or received first

0 = MSB is sent or received first

bit 4 CPOL: Clock Polarity Select bit

1 = Active-low SQICLK (SQICLK high is the Idle state)

0 = Active-high SQICLK (SQICLK low is the Idle state)

bit 3 CPHA: Clock Phase Select bit

1 = SQICLK starts toggling at the start of the first data bit

0 = SQICLK starts toggling at the middle of the first data bit

bit 2-0 MODE<2:0>: Mode Select bits

111 = Reserved

•

100 = Reserved

011 = XIP mode is selected (when this mode is entered, the module behaves as if executing in place (XIP),

but uses the register data to control timing)

010 = DMA mode is selected

001 = CPU mode is selected (the module is controlled by the CPU in PIO mode. This mode is entered when

leaving Boot or XIP mode)

000 = Reserved

Note 1: This bit must be programmed as ‘1’.