Datasheet
2015 Microchip Technology Inc. Preliminary DS60001320B-page 333
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 20-3: SQI1CFG: SQI CONFIGURATION REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — CSEN<1:0>
23:16
R/W-0 U-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
SQIEN — DATAEN<1:0>
CON
FIFORST
RX
FIFORST
TX
FIFORST
RESET
15:8
U-0 r-0 r-0 R/W-0 r-0 R/W-0 R/W-0 U-0
— — — BURSTEN
(1)
—HOLDWP —
7:0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — LSBF CPOL CPHA MODE<2:0>
Legend: HC = Hardware Cleared r = Reserved
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-24 CSEN<1:0>: Chip Select Output Enable bits
11 = Chip Select 0 and Chip Select 1 are used
10 = Chip Select 1 is used (Chip Select 0 is not used)
01 = Chip Select 0 is used (Chip Select 1 is not used)
00 = Chip Select 0 and Chip Select 1 are not used
bit 23 SQIEN: SQI Enable bit
1 = SQI module is enabled
0 = SQI module is disabled
bit 22 Unimplemented: Read as ‘0’
bit 21-20 DATAEN<1:0>: Data Output Enable bits
11 = Reserved
10 = SQID3-SQID0 outputs are enabled
01 = SQID1 and SQID0 data outputs are enabled
00 = SQID0 data output is enabled
bit 19 CONFIFORST: Control FIFO Reset bit
1 = A reset pulse is generated clearing the control FIFO
0 = A reset pulse is not generated
bit 18 RXFIFORST: Receive FIFO Reset bit
1 = A reset pulse is generated clearing the receive FIFO
0 = A reset pulse is not generated
bit 17 TXFIFORST: Transmit FIFO Reset bit
1 = A reset pulse is generated clearing the transmit FIFO
0 = A reset pulse is not generated
bit 16 RESET: Software Reset Select bit
This bit is automatically cleared by the SQI module. All of the internal state machines and FIFO pointers
are reset by this reset pulse.
1 = A reset pulse is generated
0 = A reset pulse is not generated
bit 15 Unimplemented: Read as ‘0’
bit 14-13 Reserved: Must be programmed as ‘0’
Note 1: This bit must be programmed as ‘1’.