Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 331

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family

bit 17-10 READOPCODE<7:0>: Op code Value for Read Operation bits

These bits contain the 8-bit op code value for read operation.

bit 9-8 TYPEDATA<1:0>: SQI Type Data Enable bits

The boot controller will receive the data in Single Lane, Dual Lane, or Quad Lane.

11 = Reserved

10 = Quad Lane mode data is enabled

01 = Dual Lane mode data is enabled

00 = Single Lane mode data is enabled

bit 7-6 TYPEDUMMY<1:0>: SQI Type Dummy Enable bits

The boot controller will send the dummy in Single Lane, Dual Lane, or Quad Lane.

11 = Reserved

10 = Quad Lane mode dummy is enabled

01 = Dual Lane mode dummy is enabled

00 = Single Lane mode dummy is enabled

bit 5-4 TYPEMODE<1:0>: SQI Type Mode Enable bits

The boot controller will send the mode in Single Lane, Dual Lane, or Quad Lane.

11 = Reserved

10 = Quad Lane mode is enabled

01 = Dual Lane mode is enabled

00 = Single Lane mode is enabled

bit 3-2 TYPEADDR<1:0>: SQI Type Address Enable bits

The boot controller will send the address in Single Lane, Dual Lane, or Quad Lane.

11 = Reserved

10 = Quad Lane mode address is enabled

01 = Dual Lane mode address is enabled

00 = Single Lane mode address is enabled

bit 1-0 TYPECMD<1:0>: SQI Type Command Enable bits

The boot controller will send the command in Single Lane, Dual Lane, or Quad Lane.

11 = Reserved

10 = Quad Lane mode command is enabled

01 = Dual Lane mode command is enabled

00 = Single Lane mode command is enabled