Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 33
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-18: ALTERNATE ETHERNET MII PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
AERXD0 — 18 — — I ST Alternate Ethernet Receive Data 0
AERXD1 — 19 — — I ST Alternate Ethernet Receive Data 1
AERXD2 — 28 — — I ST Alternate Ethernet Receive Data 2
AERXD3 — 29 — — I ST Alternate Ethernet Receive Data 3
AERXERR — 1 — — I ST Alternate Ethernet Receive Error Input
AERXDV — 12 — — I ST Alternate Ethernet Receive Data Valid
AERXCLK — 16 — — I ST Alternate Ethernet Receive Clock
AETXD0 — 47 — — O — Alternate Ethernet Transmit Data 0
AETXD1 — 48 — — O — Alternate Ethernet Transmit Data 1
AETXD2 — 44 — — O — Alternate Ethernet Transmit Data 2
AETXD3 — 43 — — O — Alternate Ethernet Transmit Data 3
AETXERR — 35 — — O — Alternate Ethernet Transmit Error
AECOL — 42 — — I ST Alternate Ethernet Collision Detect
AECRS — 41 — — I ST Alternate Ethernet Carrier Sense
AETXCLK — 66 — — I ST Alternate Ethernet Transmit Clock
AEMDC — 70 — — O — Alternate Ethernet Management Data Clock
AEMDIO — 71 — — I/O — Alternate Ethernet Management Data
AETXEN — 67 — — O — Alternate Ethernet Transmit Enable
Legend: CMOS = CMOS-compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = Transistor-transistor Logic input buffer PPS = Peripheral Pin Select
TABLE 1-19: ALTERNATE ETHERNET RMII PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
AERXD0 43 18 — — I ST Alternate Ethernet Receive Data 0
AERXD1 46 19 — — I ST Alternate Ethernet Receive Data 1
AERXERR 51 1 — — I ST Alternate Ethernet Receive Error Input
AETXD0 57 47 — — O — Alternate Ethernet Transmit Data 0
AETXD1 56 48 — — O — Alternate Ethernet Transmit Data 1
AEMDC 30 70 — — O — Alternate Ethernet Management Data Clock
AEMDIO 49 71 — — I/O — Alternate Ethernet Management Data
AETXEN 50 67 — — O — Alternate Ethernet Transmit Enable
AEREFCLK 45 16 — — I ST Alternate Ethernet Reference Clock
AECRSDV 62 12 — — I ST Alternate Ethernet Carrier Sense Data Valid
Legend: CMOS = CMOS-compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = Transistor-transistor Logic input buffer PPS = Peripheral Pin Select