Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 321
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
bit 16 ENHBUF: Enhanced Buffer Enable bit
(1)
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
bit 15 ON: SPI/I
2
S Module On bit
1 = SPI/I
2
S module is enabled
0 = SPI/I
2
S module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters in Idle mode
0 = Continue operation in Idle mode
bit 12 DISSDO: Disable SDOx pin bit
(4)
1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0 = SDOx pin is controlled by the module
bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits
When AUDEN =
1:
MODE32 MODE16 Communication
1124-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
1032-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
0116-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame
0016-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame
When AUDEN =
0:
MODE32 MODE16 Communication
1x32-bit
0116-bit
008-bit
bit 9 SMP: SPI Data Input Sample Phase bit
Master mode (MSTEN =
1):
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode (MSTEN =
0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
bit 8 CKE: SPI Clock Edge Select bit
(2)
1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
bit 7 SSEN: Slave Select Enable (Slave mode) bit
1 = SSx
pin used for Slave mode
0 = SSx
pin not used for Slave mode, pin controlled by port function.
bit 6 CKP: Clock Polarity Select bit
(3)
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
REGISTER 19-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED)
Note 1: This bit can only be written when the ON bit = 0. Refer to Section 37.0 “Electrical Characteristics” for
maximum clock frequency requirements.
2: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
3: When AUDEN = 1, the SPI/I
2
S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
4: This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
Section 12.4 “Peripheral Pin Select (PPS)” for more information).