Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 317
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
19.0 SERIAL PERIPHERAL
INTERFACE (SPI) AND
INTER-IC SOUND (I
2
S)
The SPI/I
2
S module is a synchronous serial interface
that is useful for communicating with external
peripherals and other microcontroller devices, as well
as digital audio devices. These peripheral devices may
be Serial EEPROMs, Shift registers, display drivers,
Analog-to-Digital Converters (ADC), etc.
The SPI/I
2
S module is compatible with Motorola
®
SPI
and SIOP interfaces.
Key features of the SPI module include:
• Master and Slave modes support
• Four different clock formats
• Enhanced Framed SPI protocol support
• User-configurable 8-bit, 16-bit and 32-bit data width
• Separate SPI FIFO buffers for receive and transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/16/8-bit data width
• Programmable interrupt event on every 8-bit, 
16-bit and 32-bit data transfer
• Operation during Sleep and Idle modes
• Audio Codec Support:
-I
2
S protocol
- Left-justified
- Right-justified
-PCM
FIGURE 19-1: SPI/I
2
S MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MZ EF family of devices. It is
not intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section 23.
“Serial Peripheral Interface (SPI)”
(DS60001106) in the “PIC32 Family Refer
-
ence Manual”, which is available from the
Microchip web site (www.microchip.com/
PIC32).
Internal
Data Bus
SDIx
SDOx
SSx
/FSYNC
SCKx
SPIxSR
bit 0
Shift
Control
Edge
Select
MSTEN
Baud Rate
Slave Select
Sync Control
Clock
Control
Transmit
Receive
and Frame
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
FIFOs Share Address SPIxBUF
SPIxBUF
Generator
PBCLK2
WriteRead
SPIxTXB FIFO
SPIxRXB FIFO
REFCLKO1
MCLKSEL