Datasheet
2015 Microchip Technology Inc. Preliminary DS60001320B-page 307
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
17.0 INPUT CAPTURE
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
The Input Capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin.
Capture events are caused by the following:
• Capture timer value on every edge (rising and falling),
specified edge first
• Prescaler capture event modes:
- Capture timer value on every 4th rising edge of
input at ICx pin
- Capture timer value on every 16th rising edge of
input at ICx pin
Each input capture channel can select between one of
six 16-bit timers for the time base, or two of six 16-bit
timers together to form a 32-bit timer. The selected
timer can use either an internal or external clock.
Other operational features include:
• Device wake-up from capture pin during Sleep and
Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values; Interrupt
optionally generated after 1, 2, 3, or 4 buffer
locations are filled
• Input capture can also be used to provide additional
sources of external interrupts
FIGURE 17-1: INPUT CAPTURE BLOCK DIAGRAM
Note: This data sheet summarizes the fea-
tures of the PIC32MZ EF family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 15. “Input Cap
-
ture” (DS60001122) of the “PIC32 Fam-
ily Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
FIFO Control
ICxBUF
(1)
Timerx
(2)
CaptureEvent
/N
FIFO
ICI<1:0>
ICM<2:0>
ICM<2:0>
101
100
011
010
001
001
111
To CPU
Set Flag ICxIF
(1)
(In IFSx Register)
Rising Edge Mode
Prescaler Mode
(4th Rising Edge)
FallingEdgeMode
Edge Detection
Prescaler Mode
(16th Rising Edge)
Sleep/Idle
Wake-up Mode
C32/ICTMR
ICx
(1)
Mode
110
Specified/Every
Edge Mode
FEDGE
PBCLK3
Note 1: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
2: See Table 17-1 for Timerx and Timery selections.
Timery
(2)