Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 272 Preliminary 2015 Microchip Technology Inc.
TABLE 12-18: PORTH REGISTER MAP FOR 144-PIN DEVICES ONLY
Virtual Address
(BF86_#)
Register
Name
(1)
Bit Range
Bits
All
Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0700 ANSELH
31:16 0000
15:0 ANSH6 ANSH5 ANSH4 ANSH1 ANSH0 0073
0710 TRISH
31:16 0000
15:0 TRISH15 TRISH14 TRISH13 TRISH12 TRISH11 TRISH10 TRISH9 TRISH8 TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 FFFF
0720 PORTH
31:16 0000
15:0 RH15 RH14 RH13 RH12 RH11 RH10 RH9 RH8 RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 xxxx
0730 LATH
31:16 0000
15:0 LATH15 LATH14 LATH13 LATH12 LATH11 LATH10 LATH9 LATH8 LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx
0740 ODCH
31:16 0000
15:0 ODCH15 ODCH14 ODCH13 ODCH12 ODCH11 ODCH10 ODCH9 ODCH8 ODCH7 ODCH6 ODCH5 ODCH4 ODCH3 ODCH2 ODCH1 ODCH0 0000
0750 CNPUH
31:16 0000
15:0 CNPUH15 CNPUH14 CNPUH13 CNPUH12 CNPUH11 CNPUH10 CNPUH9 CNPUH8 CNPUH7 CNPUH6 CNPUH5 CNPUH4 CNPUH3 CNPUH2 CNPUH1 CNPUH0 0000
0760 CNPDH
31:16 0000
15:0 CNPDH15 CNPDH14 CNPDH13 CNPDH12 CNPDH11 CNPDH10 CNPDH9 CNPDH8 CNPDH7 CNPDH6 CNPDH5 CNPDH4 CNPDH3 CNPDH2 CNPDH1 CNPDH0 0000
0770 CNCONH
31:16 0000
15:0 ON SIDL
EDGE
DETECT
0000
0780 CNENH
31:16 0000
15:0 CNENH15 CNENH14 CNENH13 CNENH12 CNENH11 CNENH10 CNENH9 CNENH8 CNENH7 CNENH6 CNENH5 CNENH4 CNENH3 CNENH2 CNENH1 CNENH0 0000
0790 CNSTATH
31:16 0000
15:0
CN
STATH15
CN
STATH14
CN
STATH13
CN
STATH12
CN
STATH11
CN
STATH10
CN
STATH9
CN
STATH8
CN
STATH7
CN
STATH6
CN
STATH5
CN
STATH4
CN
STATH3
CN
STATH2
CN
STATH1
CN
STATH0
0000
07A0 CNNEH
31:16 0000
15:0 CNNEH15 CNNEH14 CNNEH13 CNNEH12 CNNEH11 CNNEH10 CNNEH9 CNNEH8 CNNEH7 CNNEH6 CNNEH5 CNNEH4 CNNEH3 CNNEH2 CNNEH1 CNNEH0 0000
07B0 CNFH
31:16 0000
15:0 CNFH15 CNFH14 CNFH13 CNFH12 CNFH11 CNFH10 CNFH9 CNFH8 CNFH7 CNFH6 CNFH5 CNFH4 CNFH3 CNFH2 CNFH1 CNFH0 0000
Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0; Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for
more information.