Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 262 Preliminary 2015 Microchip Technology Inc.
TABLE 12-8: PORTD REGISTER MAP FOR 124-PIN AND 144-PIN DEVICES ONLY
Virtual Address
(BF86_#)
Register
Name
(1)
Bit Range
Bits
All
Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0300 ANSELD
31:16 0000
15:0 ANSD15 ANSD14 C000
0310 TRISD
31:16 0000
15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FEFF
0320 PORTD
31:16 0000
15:0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx
0330 LATD
31:16 0000
15:0 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx
0340 ODCD
31:16 0000
15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000
0350 CNPUD
31:16 0000
15:0 CNPUD15 CNPUD14 CNPUD13 CNPUD12 CNPUD11 CNPUD10 CNPUD9 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000
0360 CNPDD
31:16 0000
15:0 CNPDD15 CNPDD14 CNPDD13 CNPDD12 CNPDD11 CNPDD10 CNPDD9 CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000
0370 CNCOND
31:16 0000
15:0 ON SIDL
EDGE
DETECT
0000
0380 CNEND
31:16 0000
15:0 CNEND15 CNEND14 CNEND13 CNEND12 CNEND11 CNEND10 CNEND9 CNEND7 CNEND6 CNEND5 CNEND4 CNEND3 CNEND2 CNEND1 CNEND0 0000
0390 CNSTATD
31:16 0000
15:0
CN
STATD15
CN
STATD14
CN
STATD13
CN
STATD12
CN
STATD11
CN
STATD10
CN
STATD9
CN
STATD7
CN
STATD6
CN
STATD5
CN
STATD4
CN
STATD3
CN
STATD2
CN
STATD1
CN
STATD0
0000
03A0 CNNED
31:16 0000
15:0
CNNED15 CNNED14 CNNED13 CNNED12 CNNED11 CNNED10 CNNED9 CNNED7 CNNED6 CNNED5 CNNED4 CNNED3 CNNED2 CNNED1 CNNED0
0000
03B0 CNFD
31:16 0000
15:0 CNFD15 CNFD14 CNFD13 CNFD12 CNFD11 CNFD10 CNFD9 CNFD7 CNFD6 CNFD5 CNFD4 CNFD3 CNFD2 CNFD1 CNFD0 0000
Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for
more information.