Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 251
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
12.2 Registers for Slew Rate Control
Some I/O pins can be configured for various types of
slew rate control on its associated port. This is
controlled by the Slew Rate Control bits in the
SRCON1x and SRCON0x registers that are associated
with each I/O port. The slew rate control is configured
using the corresponding bit in each register, as shown
in Table 12-1.
As an example, writing 0x0001, 0x0000 to SRCON1A
and SRCON0A, respectively, will enable slew rate
control on the RA0 pin and sets the slew rate to the
slow edge rate.
TABLE 12-1: SLEW RATE CONTROL BIT
SETTINGS
12.3 CLR, SET, and INV Registers
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
12.4 Peripheral Pin Select (PPS)
A major challenge in general purpose devices is provid-
ing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. The chal
-
lenge is even greater on low pin-count devices. In an
application where more than one peripheral needs to
be assigned to a single pin, inconvenient workarounds
in application code or a complete redesign may be the
only option.
PPS configuration provides an alternative to these
choices by enabling peripheral set selection and their
placement on a wide range of I/O pins. By increasing
the pinout options available on a particular device,
users can better tailor the device to their entire
application, rather than trimming the application to fit
the device.
The PPS configuration feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of most digital peripherals
to these I/O pins. PPS is performed in software and
generally does not require the device to be repro
-
grammed. Hardware safeguards are included that pre-
vent accidental or spurious changes to the peripheral
mapping once it has been established.
12.4.1 AVAILABLE PINS
The number of available pins is dependent on the
particular device and its pin count. Pins that support the
PPS feature include the designation “RPn” in their full
pin designation, where “RP” designates a remappable
peripheral and “n” is the remappable port number.
12.4.2 AVAILABLE PERIPHERALS
The peripherals managed by the PPS are all digital-
only peripherals. These include general serial
communications (UART, SPI, and CAN), general pur
-
pose timer clock inputs, timer-related peripherals (input
capture and output compare), interrupt-on-change
inputs, and reference clocks (input and output).
In comparison, some digital-only peripheral modules
are never included in the PPS feature. This is because
the peripheral’s function requires special I/O circuitry
on a specific port and cannot be easily connected to
multiple pins. These modules include I
2
C among oth-
ers. A similar requirement excludes all modules with
analog inputs, such as the Analog-to-Digital Converter
(ADC).
A key difference between remappable and non-remap-
pable peripherals is that remappable peripherals are
not associated with a default I/O pin. The peripheral
must always be assigned to a specific I/O pin before it
can be used. In contrast, non-remappable peripherals
are always available on a default pin, assuming that the
peripheral is active and not conflicting with another
peripheral.
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
SRCON1x SRCON0x Description
1 1 Slew rate control is enabled
and is set to the slowest
edge rate.
1 0 Slew rate control is enabled
and is set to the slow edge
rate.
0 1 Slew rate control is enabled
and is set to the medium
edge rate.
0 0 Slew rate control is disabled
and is set to the fastest
edge rate.
Note: By default, all of the Port pins are set to
the fastest edge rate.