Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 243
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 11-28: USBLPMR1: USB LINK POWER MANAGEMENT CONTROL 
REGISTER 1
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — LPMERRIE LPMRESIE LPMACKIE LPMNYIE LPMSTIE LPMTOIE
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC
— — — LPMNAK LPMEN<1:0> LPMRES LPMXMT
15:8
R-0 R-0 R-0 R-0 U-0 U-0 U-0 R-0
ENDPOINT<3:0> — — —RMTWAK
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
HIRD<3:0> LNKSTATE<3:0>
Legend: HC = Hardware Cleared
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29
LPMERRIE: LPM Error Interrupt Enable bit
1 = LPMERR interrupt is enabled
0 = LPMERR interrupt is disabled
bit 28
LPMRESIE: LPM Resume Interrupt Enable bit
1 = LPMRES interrupt is enabled
0 = LPMRES interrupt is disabled
bit 27
LPMACKIE: LPM Acknowledge Interrupt Enable bit
1 = Enable the LPMACK Interrupt
0 = Disable the LPMACK Interrupt
bit 26
LPMNYIE: LPM NYET Interrupt Enable bit
1 = Enable the LPMNYET Interrupt
0 = Disable the LPMNYET Interrupt
bit 25
LPMSTIE: LPM STALL Interrupt Enable bit
1 = Enable the LPMST Interrupt
0 = Disable the LPMST Interrupt
bit 24
LPMTOIE: LPM Time-out Interrupt Enable bit
1 = Enable the LPMTO Interrupt
0 = Disable the LPMTO Interrupt
bit 23-21
Unimplemented: Read as ‘0’
bit 20
LPMNAK: LPM-only Transaction Setting bit
1 = All endpoints will respond to all transactions other than a LPM transaction with a NAK
0 = Normal transaction operation
Setting this bit to ‘1’ will only take effect after the USB module as been LPM suspended.
bit 19-18
LPMEN<1:0>: LPM Enable bits (Device mode)
11 = LPM Extended transactions are supported
10 = LPM and Extended transactions are not supported
01 = LPM mode is not supported but Extended transactions are supported
00 = LPM Extended transactions are supported
bit 17
LPMRES: LPM Resume bit
1 = Initiate resume (remote wake-up). Resume signaling is asserted for 50 µs.
0 = No resume operation
This bit is self-clearing.