Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 235
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 11-17: USBEOFRST: USB END-OF-FRAME/SOFT RESET CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — NRSTX NRST
23:16
R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R.W-0 R/W-1 R/W-0
LSEOF<7:0>
15:8
R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R.W-1 R/W-1 R/W-1
FSEOF<7:0>
7:0
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R.W-0 R/W-0 R/W-0
HSEOF<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-26
Unimplemented: Read as ‘0’
bit 25
NRSTX: Reset of XCLK Domain bit
1 = Reset the XCLK domain, which is clock recovered from the received data by the PHY
0 = Normal operation
bit 24
NRST: Reset of CLK Domain bit
1 = Reset the CLK domain, which is clock recovered from the peripheral bus
0 = Normal operation
bit 23-16
LSEOF<7:0>: Low-Speed EOF bits
These bits set the Low-Speed transaction in units of 1.067 µs (default setting is 121.6 µs) prior to the EOF
to stop new transactions from beginning.
bit 15-8
FSEOF<7:0>: Full-Speed EOF bits
These bits set the Full-Speed transaction in units of 533.3 µs (default setting is 63.46 µs) prior to the EOF
to stop new transactions from beginning.
bit 7-0
HSEOF<7:0>: Hi-Speed EOF bits
These bits set the Hi-Speed transaction in units of 133.3 µs (default setting is 17.07µs) prior to the EOF to
stop new transactions from beginning.