Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family

DS60001320B-page 224 Preliminary  2015 Microchip Technology Inc.

bit 18

OVERRUN: Data Overrun Status bit (Device mode)

1 = An OUT packet cannot be loaded into the RX FIFO.

0 = Written by software to clear this bit

This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero.

ERROR: No Data Packet Received Status bit (Host mode)

1 = Three attempts have been made to receive a packet and no data packet has been received. An interrupt

is generated.

0 = Written by the software to clear this bit.

This bit is only valid when the RX endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always

returns zero.

bit 17

FIFOFULL: FIFO Full Status bit

1 = No more packets can be loaded into the RX FIFO

0 = The RX FIFO has at least one free space

bit 16

RXPKTRDY: Data Packet Reception Status bit

1 = A data packet has been received. An interrupt is generated.

0 = Written by software to clear this bit when the packet has been unloaded from the RX FIFO.

bit 15-11

MULT<4:0>: Multiplier Control bits

For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT+1

for the payload size.

For Bulk endpoints, MULT can be up to 32 and defines the number of “USB” packets of the specified payload

into which a single data packet placed in the FIFO should be split, prior to transfer. The data packet is required

to be an exact multiple of the payload specified by TXMAXP.

For Isochronous/Interrupts endpoints operating in Hi-Speed mode, MULT may be either 2 or 3 and specifies

the maximum number of such transactions that can take place in a single microframe.

bit 10-0

RXMAXP<10:0>: Maximum RX Payload Per Transaction Control bits

This field sets the maximum payload (in bytes) transmitted in a single transaction. The value is subject to the

constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in

Full-Speed and Hi-Speed operations.

RXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1.

(ENDPOINT 1-7) (CONTINUED)