Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 222 Preliminary  2015 Microchip Technology Inc.
REGISTER 11-9: USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1
(ENDPOINT 1-7)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HC R-0 R/W-0
AUTOCLR
ISO
DMAREQEN
DISNYET
DMAREQMD
— —
INCOMPRX
AUTORQ PIDERR DATATWEN DATATGGL
23:16
R/W-0, HC R/W-0, HS R/W-0 R/W-0, HC R-0, HS R/W-0, HS R-0, HS, HC R/W-0, HS
CLRDT
SENTSTALL SENDSTALL
FLUSH
DATAERR OVERRUN
FIFOFULL RXPKTRDY
RXSTALL REQPKT DERRNAKT ERROR
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MULT<4:0> RXMAXP<10:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RXMAXP<7:0>
Legend: HC = Hardware Cleared HS = Hardware Set
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31
AUTOCLR: RXPKTRDY Automatic Clear Control bit
1 = RXPKTRDY will be automatically cleared when a packet of RXMAXP bytes has been unloaded from the
RX FIFO. When packets of less than the maximum packet size are unloaded, RXPKTRDY will have to be
cleared manually. When using a DMA to unload the RX FIFO, data is read from the RX FIFO in 4-byte
chunks regardless of the RXMAXP.
0 = No automatic clearing of RXPKTRDY
This bit should not be set for high-bandwidth Isochronous endpoints.
bit 30
ISO: Isochronous Endpoint Control bit (Device mode)
1 = Enable the RX endpoint for Isochronous transfers
0 = Enable the RX endpoint for Bulk/Interrupt transfers
AUTORQ: Automatic Packet Request Control bit (Host mode)
1 = REQPKT will be automatically set when RXPKTRDY bit is cleared.
0 = No automatic packet request
This bit is automatically cleared when a short packet is received.
bit 29
DMAREQEN: DMA Request Enable Control bit
1 = Enable DMA requests for the RX endpoint.
0 = Disable DMA requests for the RX endpoint.
bit 28
DISNYET: Disable NYET Handshakes Control/PID Error Status bit (Device mode)
1 = In Bulk/Interrupt transactions, disables the sending of NYET handshakes. All successfully received RX
packets are ACKed including at the point at which the FIFO becomes full.
0 = Normal operation.
In Bulk/Interrupt transactions, this bit only has any effect in Hi-Speed mode, in which mode it should be set for
all Interrupt endpoints.
PIDERR: PID Error Status bit (Host mode)
1 = In ISO transactions, this indicates a PID error in the received packet.
0 = No error
bit 27
DMAREQMD: DMA Request Mode Selection bit
1 = DMA Request Mode 1
0 = DMA Request Mode 0