Datasheet

ManualsBrandsMicrochip ManualsEmbedded Processors & ControllersMicrocontroller 32 Bit TQFP-64

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PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family

DS60001320B-page 216 Preliminary  2015 Microchip Technology Inc.

bit 21

SENDSTALL: Send Stall Control bit (Device mode)

1 = Terminate the current transaction and transmit a STALL handshake. This bit is automatically cleared.

0 = Do not send STALL handshake.

REQPKT: IN transaction Request Control bit (Host mode)

1 = Request an IN transaction. This bit is cleared when the RXPKTRDY bit is set.

0 = Do not request an IN transaction

bit 20

SETUPEND: Early Control Transaction End Status bit (Device mode)

1 = A control transaction ended before the DATAEND bit has been set. An interrupt will be generated and

the FIFO flushed at this time.

0 = Normal operation

This bit is cleared by writing a ‘1’ to the SVCSETEND bit in this register.

ERROR: No Response Error Status bit (Host mode)

1 = Three attempts have been made to perform a transaction with no response from the peripheral. An inter-

rupt is generated.

0 = Clear this flag. Software must write a ‘0’ to this bit to clear it.

bit 19

DATAEND: End of Data Control bit (Device mode)

The software sets this bit when:

• Setting TXPKTRDY for the last data packet

• Clearing RXPKTRDY after unloading the last data packet

• Setting TXPKTRDY for a zero length data packet

Hardware clears this bit.

SETUPPKT: Send a SETUP token Control bit (Host mode)

1 = When set at the same time as the TXPKTRDY bit is set, the module sends a SETUP token instead of an

OUT token for the transaction

0 = Normal OUT token operation

Setting this bit also clears the Data Toggle.

bit 18

SENTSTALL: STALL sent status bit (Device mode)

1 = STALL handshake has been transmitted

0 = Software clear of bit

RXSTALL: STALL handshake received Status bit (Host mode)

1 = STALL handshake was received

0 = Software clear of bit

bit 17

TXPKTRDY: TX Packet Ready Control bit

1 = Data packet has been loaded into the FIFO. It is cleared automatically.

0 = No data packet is ready for transmit

bit 16

RXPKTRDY: RX Packet Ready Status bit

1 = Data packet has been received. Interrupt is generated (when enabled) when this bit is set.

0 = No data packet has been received

This bit is cleared by setting the SVCRPR bit.

bit 15-0

Unimplemented: Read as ‘0’

(ENDPOINT 0) (CONTINUED)