Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 215
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 11-5: USBIE0CSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0
(ENDPOINT 0)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 R/W-0 R/W-0, HC R/W-0 R/W-0, HC
— — — —
— — —
FLSHFIFO
DISPING DTWREN DATATGGL
23:16
R/W-0, HC R/W-0, HC R/W-0, HC R/C-0, HS R/W-0, HS R-0, HS R-0 R-0
SVCSETEND SVCRPR SENDSTALL SETUPEND DATAEND SENTSTALL
TXPKTRDY RXPKTRDY
NAKTMOUT STATPKT REQPKT ERROR SETUPPKT RXSTALL
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend: HC = Hardware Cleared HS = Hardware Set
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28
Unimplemented: Read as ‘0’
bit 27
DISPING: Disable Ping tokens control bit (Host mode)
1 = USB Module will not issue PING tokens in data and status phases of a Hi-Speed Control transfer
0 = Ping tokens are issued
bit 26
DTWREN: Data Toggle Write Enable bit (Host mode)
1 = Enable the current state of the Endpoint 0 data toggle to be written. Automatically cleared.
0 = Disable data toggle write
bit 25
DATATGGL: Data Toggle bit (Host mode)
When read, this bit indicates the current state of the Endpoint 0 data toggle.
If DTWREN = 1, this bit is writable with the desired setting.
If DTWREN = 0, this bit is read-only.
bit 24
FLSHFIFO: Flush FIFO Control bit
1 = Flush the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO pointer is reset and
the TXPKTRDY/RXPKTRDY bit is cleared. Automatically cleared when the operation completes. Should
only be used when TXPKTRDY/RXPKTRDY = 1.
0 = No Flush operation
bit 23
SVCSETEND: Clear SETUPEND Control bit (Device mode)
1 = Clear the SETUPEND bit in this register. This bit is automatically cleared.
0 = Do not clear
NAKTMOUT: NAK Time-out Control bit (Host mode)
1 = Endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the
NAKLIM<4:0> bits (USBICSR<28:24>)
0 = Allow the endpoint to continue
bit 22
SVCRPR: Serviced RXPKTRDY Clear Control bit (Device mode)
1 = Clear the RXPKTRDY bit in this register. This bit is automatically cleared.
0 = Do not clear
STATPKT: Status Stage Transaction Control bit (Host mode)
1 = When set at the same time as the TXPKTRDY or REQPKT bit is set, performs a status stage transaction
0 = Do not perform a status stage transaction