Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 208 Preliminary  2015 Microchip Technology Inc.
REGISTER 11-1: USBCSR0: USB CONTROL STATUS REGISTER 0
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS
EP7TXIF EP6TXIF EP5TXIF EP4TXIF EP3TXIF EP2TXIF EP1TXIF EP0IF
15:8
R/W-0 R/W-0 R/W-1 R-0, HS R-0 R/W-0 R-0, HC R/W-0
ISOUPD SOFTCONN HSEN HSMODE RESET RESUME SUSPMODE SUSPEN
— —
7:0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—
FUNC<6:0>
— — — — — — —
Legend: HS = Hardware Set HC = Hardware Cleared
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-17 EP7TXIF:EP1TXIF: Endpoint ‘n’ TX Interrupt Flag bit
1 = Endpoint has a transmit interrupt to be serviced
0 = No interrupt event
bit 16 EP0IF: Endpoint 0 Interrupt bit
1 = Endpoint 0 has an interrupt to be serviced
0 = No interrupt event
All EPxTX and EP0 bits are cleared when the byte is read. Therefore, these bits must be read independently
from the remaining bits in this register to avoid accidental clearing.
bit 15 ISOUPD: ISO Update bit (Device mode only; unimplemented in Host mode)
1 = USB module will wait for a SOF token from the time TXPKTRDY is set before sending the packet
0 = No change in behavior
This bit only affects endpoints performing isochronous transfers when in Device mode. This bit is
unimplemented in Host mode.
bit 14 SOFTCONN: Soft Connect/Disconnect Feature Selection bit
1 = The USB D+/D- lines are enabled and active
0 = The USB D+/D- lines are disabled and are tri-stated
This bit is only available in Device mode.
bit 13 HSEN: Hi-Speed Enable bit
1 = The USB module will negotiate for Hi-Speed mode when the device is reset by the hub
0 = Module only operates in Full-Speed mode
bit 12 HSMODE: Hi-Speed Mode Status bit
1 = Hi-Speed mode successfully negotiated during USB reset
0 = Module is not in Hi-Speed mode
In Device mode, this bit becomes valid when a USB reset completes. In Host mode, it becomes valid when
the RESET bit is cleared.
bit 11 RESET: Module Reset Status bit
1 = Reset signaling is present on the bus
0 = Normal module operation
In Device mode, this bit is read-only. In Host mode, this bit is read/write.