Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 173
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 9-1: PRECON: PREFETCH MODULE CONTROL REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
U-0
— — — — — PFMSECEN — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
— — PREFEN<1:0> —PFMWS<2:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26 PFMSECEN: Flash SEC Interrupt Enable bit
1 = Generate an interrupt when the PFMSEC bit (PRESTAT<26>) is set
0 = Do not generate an interrupt when the PFMSEC bit is set
bit 25-6 Unimplemented: Read as ‘0’
bit 5-4 PREFEN<1:0>: Predictive Prefetch Enable bits
11 = Enable predictive prefetch for any address
10 = Enable predictive prefetch for CPU instructions and CPU data
01 = Enable predictive prefetch for CPU instructions only
00 = Disable predictive prefetch
bit 3 Unimplemented: Read as ‘0’
bit 2-0 PFMWS<2:0>: PFM Access Time Defined in Terms of SYSCLK Wait States bits
(1)
111 = Seven Wait states
•
•
•
010 = Two Wait states
001 = One Wait state
000 = Zero Wait states
Note 1: For the Wait states to SYSCLK relationship, refer to Table 37-13 in Section37.0 “Electrical
Characteristics”.