Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 171
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
9.0 PREFETCH MODULE
The Prefetch module is a performance enhancing
module that is included in PIC32MZ EF family devices.
When running at high-clock rates, Wait states must be
inserted into Program Flash Memory (PFM) read
transactions to meet the access time of the PFM. Wait
states can be hidden to the core by prefetching and
storing instructions in a temporary holding area that the
CPU can access quickly. Although the data path to the
CPU is 32 bits wide, the data path to the PFM is 128
bits wide. This wide data path provides the same
bandwidth to the CPU as a 32-bit path running at four
times the frequency.
The Prefetch module holds a subset of PFM in
temporary holding spaces known as lines. Each line
contains a tag and data field. Normally, the lines hold a
copy of what is currently in memory to make
instructions or data available to the CPU without Flash
Wait states.
Key features include:
• 4x16 byte fully-associative lines
• One line for CPU instructions
• One line for CPU data
• Two lines for peripheral data
• 16-byte parallel memory fetch
• Configurable predictive prefetch
• Error detection and correction
A simplified block diagram of the Prefetch module is
shown in
Figure 9-1.
FIGURE 9-1: PREFETCH MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MZ EF family of devices. It is
not intended to be a comprehensive refer
-
ence source. To complement the informa-
tion in this data sheet, refer to Section 41.
“Prefetch Module for Devices with L1
CPU Cache” (DS60001183) in the “PIC32
Family Reference Manual”
, which is avail-
able from the Microchip web site
(www.microchip.com/PIC32).
Bus Control
Prefetch Buffer
Line Control
Tag
Data
Program Flash Memory (PFM)
CPU
CPU
SYSCLK