Datasheet
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 168 Preliminary 2015 Microchip Technology Inc.
REGISTER 8-7: SLEWCON: OSCILLATOR SLEW CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — SYSDIV<3:0>
(1)
15:8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1 R/W-0
— — — — —SLWDIV<2:0>
7:0
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R-0, HS, HC
— — — — — UPEN DNEN BUSY
Legend: HC = Hardware Cleared HS = Hardware Set
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19-16 SYSDIV<3:0>: System Clock Divide Control bits
(1)
1111 = SYSCLK is divided by 16
1110 = SYSCLK is divided by 15
•
•
•
0010 = SYSCLK is divided by 3
0001 = SYSCLK is divided by 2
0000 = SYSCLK is not divided
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8 SLWDIV<2:0>: Slew Divisor Steps Control bits
These bits control the maximum division steps used when slewing during a frequency change.
111 = Steps are divide by 128, 64, 32, 16, 8, 4, 2, and then no divisor
110 = Steps are divide by 64, 32, 16, 8, 4, 2, and then no divisor
101 = Steps are divide by 32, 16, 8, 4, 2, and then no divisor
100 = Steps are divide by 16, 8, 4, 2, and then no divisor
011 = Steps are divide by 8, 4, 2, and then no divisor
010 = Steps are divide by 4, 2, and then no divisor
001 = Steps are divide by 2, and then no divisor
000 = No divisor is used during slewing
Note: The steps apply in reverse order (i.e., 2, 4, 8, etc.) during a downward frequency change.
bit 7-3 Unimplemented: Read as ‘0’
bit 2 UPEN: Upward Slew Enable bit
1 = Slewing enabled for switching to a higher frequency
0 = Slewing disabled for switching to a higher frequency
bit 1 DNEN: Downward Slew Enable bit
1 = Slewing enabled for switching to a lower frequency
0 = Slewing disabled for switching to a lower frequency
bit 0 BUSY: Clock Switching Slewing Active Status bit
1 = Clock frequency is being actively slewed to the new frequency
0 = Clock switch has reached its final value
Note 1: The SYSDIV<3:0> bit settings are ignored if both UPEN and DNEN = 0, and SYSCLK will be divided by 1.